From: Ferruh Yigit <ferruh.yigit@amd.com>
To: Jiawen Wu <jiawenwu@trustnetic.com>, dev@dpdk.org
Subject: Re: [PATCH] net/txgbe: fix a mass of interrupts
Date: Mon, 18 Nov 2024 19:59:17 +0000 [thread overview]
Message-ID: <ff803425-d546-4502-b695-75cd60c59181@amd.com> (raw)
In-Reply-To: <20241115083336.1195101-1-jiawenwu@trustnetic.com>
On 11/15/2024 8:33 AM, Jiawen Wu wrote:
> Since firmware version 0x20010, GPIO interrupt enable is set to 0xd by
> default, which means enable bit 0 'tx_fault'. And GPIO interrupt polarity
> is set to 0xd by default too, which means these interrupts are rising-edge
> sensitive.
>
> So when unplug the SFP module, GPIO line 0 'tx_fault' is 0 -> 1 triggers
> the interrupt. However, the interrupt is not cleared. And GPIO interrupt
> mask is enabled and disabled to trigger the MISC interrupt repeatedly.
>
> Since this 'tx_fault' interrupt does not make much sense, simply clear it
> to fix the issue.
>
> Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
>
Hi Jiawen,
Can you please provide a fixes tag?
Also I believe you would like to backport this fix, if so please add the
stable tag as well.
prev parent reply other threads:[~2024-11-18 19:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-15 8:33 Jiawen Wu
2024-11-18 19:59 ` Ferruh Yigit [this message]
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