[PATCH] net/txgbe: fix a mass of interrupts

[PATCH] net/txgbe: fix a mass of interrupts

[Jiawen Wu]

Since firmware version 0x20010, GPIO interrupt enable is set to 0xd by
default, which means enable bit 0 'tx_fault'. And GPIO interrupt polarity
is set to 0xd by default too, which means these interrupts are rising-edge
sensitive.

So when unplug the SFP module, GPIO line 0 'tx_fault' is 0 -> 1 triggers
the interrupt. However, the interrupt is not cleared. And GPIO interrupt
mask is enabled and disabled to trigger the MISC interrupt repeatedly.

Since this 'tx_fault' interrupt does not make much sense, simply clear it
to fix the issue.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/txgbe/txgbe_ethdev.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index a956216abb..ea9faba2c0 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -1555,6 +1555,9 @@ static void txgbe_reinit_gpio_intr(struct txgbe_hw *hw)
 	wr32(hw, TXGBE_GPIOINTMASK, 0xFF);
 	reg = rd32(hw, TXGBE_GPIORAWINTSTAT);
 
+	if (reg & TXGBE_GPIOBIT_0)
+		wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_0);
+
 	if (reg & TXGBE_GPIOBIT_2)
 		wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_2);
 
@@ -2796,6 +2799,8 @@ txgbe_dev_sfp_event(struct rte_eth_dev *dev)
 
 	wr32(hw, TXGBE_GPIOINTMASK, 0xFF);
 	reg = rd32(hw, TXGBE_GPIORAWINTSTAT);
+	if (reg & TXGBE_GPIOBIT_0)
+		wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_0);
 	if (reg & TXGBE_GPIOBIT_2) {
 		wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_2);
 		rte_eal_alarm_set(1000 * 100, txgbe_dev_detect_sfp, dev);
-- 
2.27.0

Re: [PATCH] net/txgbe: fix a mass of interrupts

[Ferruh Yigit]

On 11/15/2024 8:33 AM, Jiawen Wu wrote:
> Since firmware version 0x20010, GPIO interrupt enable is set to 0xd by
> default, which means enable bit 0 'tx_fault'. And GPIO interrupt polarity
> is set to 0xd by default too, which means these interrupts are rising-edge
> sensitive.
> 
> So when unplug the SFP module, GPIO line 0 'tx_fault' is 0 -> 1 triggers
> the interrupt. However, the interrupt is not cleared. And GPIO interrupt
> mask is enabled and disabled to trigger the MISC interrupt repeatedly.
> 
> Since this 'tx_fault' interrupt does not make much sense, simply clear it
> to fix the issue.
> 
> Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
>

Hi Jiawen,

Can you please provide a fixes tag?
Also I believe you would like to backport this fix, if so please add the
stable tag as well.