* [dts] [PATCH V2 1/2] tests/unit_tests_eal: modify code to adapt avx512
@ 2021-11-02 6:18 Xiang An
2021-11-02 6:18 ` [dts] [PATCH V2 2/2] tests/l3fwdacl: " Xiang An
0 siblings, 1 reply; 2+ messages in thread
From: Xiang An @ 2021-11-02 6:18 UTC (permalink / raw)
To: dts; +Cc: xiangx.an
Modify code to adapt rxmod avx512.
Signed-off-by: Xiang An <xiangx.an@intel.com>
---
tests/TestSuite_unit_tests_eal.py | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/tests/TestSuite_unit_tests_eal.py b/tests/TestSuite_unit_tests_eal.py
index 8096183..b5cb7a2 100644
--- a/tests/TestSuite_unit_tests_eal.py
+++ b/tests/TestSuite_unit_tests_eal.py
@@ -38,7 +38,7 @@ EAL autotest.
import framework.utils as utils
from framework.test_case import TestCase
-
+from framework.settings import load_global_setting, DPDK_RXMODE_SETTING
#
#
# Test class.
@@ -462,7 +462,8 @@ class TestUnitTestsEal(TestCase):
self.test_app_cmdline += "--no-pci"
if self.dut.dpdk_version >= '20.11.0':
- self.test_app_cmdline += " --force-max-simd-bitwidth=0"
+ if load_global_setting(DPDK_RXMODE_SETTING) == 'default':
+ self.test_app_cmdline += " --force-max-simd-bitwidth=0"
self.dut.send_expect(self.test_app_cmdline, "R.*T.*E.*>.*>", self.start_test_time)
out = self.dut.send_expect("acl_autotest", "RTE>>", self.run_cmd_time)
self.dut.send_expect("quit", "# ")
--
1.8.3.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* [dts] [PATCH V2 2/2] tests/l3fwdacl: modify code to adapt avx512
2021-11-02 6:18 [dts] [PATCH V2 1/2] tests/unit_tests_eal: modify code to adapt avx512 Xiang An
@ 2021-11-02 6:18 ` Xiang An
0 siblings, 0 replies; 2+ messages in thread
From: Xiang An @ 2021-11-02 6:18 UTC (permalink / raw)
To: dts; +Cc: xiangx.an
Signed-off-by: Xiang An <xiangx.an@intel.com>
---
tests/TestSuite_l3fwdacl.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/TestSuite_l3fwdacl.py b/tests/TestSuite_l3fwdacl.py
index 65c46b0..dc5d41f 100644
--- a/tests/TestSuite_l3fwdacl.py
+++ b/tests/TestSuite_l3fwdacl.py
@@ -40,6 +40,7 @@ import time
import framework.packet as packet
import framework.utils as utils
from framework.test_case import TestCase
+from framework.settings import load_global_setting, DPDK_RXMODE_SETTING
class TestL3fwdacl(TestCase):
@@ -643,7 +644,8 @@ class TestL3fwdacl(TestCase):
print("Core mask: %s" % self.core_mask)
if self.dut.dpdk_version >= '20.11.0':
- self.eal_para += " --force-max-simd-bitwidth=0"
+ if load_global_setting(DPDK_RXMODE_SETTING) == 'default':
+ self.eal_para += " --force-max-simd-bitwidth=0"
valid_ports = [port for port in ports if self.tester.get_local_port(port) != -1]
self.verify(
--
1.8.3.1
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2021-11-02 6:18 [dts] [PATCH V2 1/2] tests/unit_tests_eal: modify code to adapt avx512 Xiang An
2021-11-02 6:18 ` [dts] [PATCH V2 2/2] tests/l3fwdacl: " Xiang An
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