From: Xiang An <xiangx.an@intel.com>
To: dts@dpdk.org
Cc: xiangx.an@intel.com
Subject: [dts] [PATCH V1 3/4] tests/l3fwdacl: modify code to adapt avx512
Date: Tue, 2 Nov 2021 14:43:17 +0800 [thread overview]
Message-ID: <1635835398-70543-3-git-send-email-xiangx.an@intel.com> (raw)
In-Reply-To: <1635835398-70543-1-git-send-email-xiangx.an@intel.com>
Modify code to adapt rxmod avx512.
Signed-off-by: Xiang An <xiangx.an@intel.com>
---
tests/TestSuite_l3fwdacl.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/TestSuite_l3fwdacl.py b/tests/TestSuite_l3fwdacl.py
index 65c46b0..dc5d41f 100644
--- a/tests/TestSuite_l3fwdacl.py
+++ b/tests/TestSuite_l3fwdacl.py
@@ -40,6 +40,7 @@ import time
import framework.packet as packet
import framework.utils as utils
from framework.test_case import TestCase
+from framework.settings import load_global_setting, DPDK_RXMODE_SETTING
class TestL3fwdacl(TestCase):
@@ -643,7 +644,8 @@ class TestL3fwdacl(TestCase):
print("Core mask: %s" % self.core_mask)
if self.dut.dpdk_version >= '20.11.0':
- self.eal_para += " --force-max-simd-bitwidth=0"
+ if load_global_setting(DPDK_RXMODE_SETTING) == 'default':
+ self.eal_para += " --force-max-simd-bitwidth=0"
valid_ports = [port for port in ports if self.tester.get_local_port(port) != -1]
self.verify(
--
1.8.3.1
next prev parent reply other threads:[~2021-11-02 6:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-02 6:43 [dts] [PATCH V1 1/4] tests/kernelpf_iavf: " Xiang An
2021-11-02 6:43 ` [dts] [PATCH V1 2/4] tests/vf_vlan: " Xiang An
2021-11-02 6:43 ` Xiang An [this message]
2021-11-02 6:43 ` [dts] [PATCH V1 4/4] tests/unit_tests_eal: " Xiang An
2021-11-02 10:43 ` Ananyev, Konstantin
2021-11-02 11:16 ` Huang, ZhiminX
2021-11-02 11:26 ` Ananyev, Konstantin
2021-11-03 3:07 ` Huang, ZhiminX
2021-11-03 10:39 ` Ananyev, Konstantin
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