From: Xiang An <xiangx.an@intel.com>
To: dts@dpdk.org
Cc: xiangx.an@intel.com
Subject: [dts][PATCH V1 1/2] tests/l3fwdacl: modify code to apapt avx512
Date: Mon, 15 Nov 2021 17:58:14 +0800 [thread overview]
Message-ID: <1636970295-178745-1-git-send-email-xiangx.an@intel.com> (raw)
Whatever the rx_mode is, all use "force-max-simd-bitwidth=0" as default parameter.
Signed-off-by: Xiang An <xiangx.an@intel.com>
---
tests/TestSuite_l3fwdacl.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/TestSuite_l3fwdacl.py b/tests/TestSuite_l3fwdacl.py
index 65c46b0c..4baae51e 100644
--- a/tests/TestSuite_l3fwdacl.py
+++ b/tests/TestSuite_l3fwdacl.py
@@ -638,7 +638,7 @@ class TestL3fwdacl(TestCase):
cores = self.get_core_list()
self.verify(cores is not None, "Insufficient cores for speed testing")
- self.eal_para = self.dut.create_eal_parameters(cores=self.get_core_list())
+ self.eal_para = self.dut.create_eal_parameters(cores=self.get_core_list(), other_eal_param='force-max-simd-bitwidth')
self.core_mask = utils.create_mask(cores)
print("Core mask: %s" % self.core_mask)
--
2.17.1
next reply other threads:[~2021-11-15 9:57 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-15 9:58 Xiang An [this message]
2021-11-15 9:58 ` [dts][PATCH V1 2/2] tests/unit_tests_eal: modify code to adapt avx512 Xiang An
2021-11-22 15:23 ` Tu, Lijuan
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