From: "Yu.Jiang" <yux.jiang@intel.com>
To: yuan.peng@intel.com, dts@dpdk.org
Cc: Yu Jiang <yux.jiang@intel.com>
Subject: [dts][PATCH V1 0/2] l3fwdacl: merge l3fwd-acl wtih l3fwd
Date: Fri, 10 Jun 2022 15:06:19 +0800 [thread overview]
Message-ID: <1654844781-6435-1-git-send-email-yux.jiang@intel.com> (raw)
From: Yu Jiang <yux.jiang@intel.com>
l3fwdacl: merge l3fwd-acl wtih l3fwd
Yu Jiang (2):
test_plans/l3fwdacl: merge l3fwd-acl wtih l3fwd
tests/l3fwdacl: merge l3fwd-acl wtih l3fwd and modify it to support different
force-max-simd-bitwidth
conf/app_name.cfg | 3 +-
test_plans/l3fwdacl_test_plan.rst | 69 +++++++++++++++++++++----------
tests/TestSuite_l3fwdacl.py | 49 +++++++++++++---------
3 files changed, 77 insertions(+), 44 deletions(-)
--
2.25.1
next reply other threads:[~2022-06-10 7:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 7:06 Yu.Jiang [this message]
2022-06-10 7:06 ` [dts][PATCH V1 1/2] test_plans/l3fwdacl: " Yu.Jiang
2022-06-10 7:06 ` [dts][PATCH V1 2/2] tests/l3fwdacl: merge l3fwd-acl wtih l3fwd and modify it to support different force-max-simd-bitwidth Yu.Jiang
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