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From: lingwei <weix.ling@intel.com>
To: dts@dpdk.org
Cc: lingwei <weix.ling@intel.com>
Subject: [dts] [dts 1/5] test_plans/nic_single_core_perf_test_plan:update test plan to sync with testcase
Date: Mon,  7 Sep 2020 15:35:28 +0000	[thread overview]
Message-ID: <20200907153532.37857-2-weix.ling@intel.com> (raw)
In-Reply-To: <20200907153532.37857-1-weix.ling@intel.com>

Signed-off-by: lingwei <weix.ling@intel.com>
---
 test_plans/nic_single_core_perf_test_plan.rst | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/test_plans/nic_single_core_perf_test_plan.rst b/test_plans/nic_single_core_perf_test_plan.rst
index 4157c31..c78abad 100644
--- a/test_plans/nic_single_core_perf_test_plan.rst
+++ b/test_plans/nic_single_core_perf_test_plan.rst
@@ -62,6 +62,13 @@ Prerequisites
 
     2 TG 25g ports for FVL25G ports
     4 TG 10g ports for 4 NNT10G ports
+
+4. Case config::
+    For FVL40g, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=y"
+    in ./config/common_base and re-build DPDK.
+
+    For FVL25G, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_ICE_16BYTE_RX_DESC=y"
+    in ./config/common_base and re-build DPDK.
     
 Test Case : Single Core Performance Measurement
 ===============================================
-- 
2.17.1


  reply	other threads:[~2020-09-07  7:56 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-07 15:35 [dts] [PATCH V2 0/5] update " lingwei
2020-09-07 15:35 ` lingwei [this message]
2020-09-07 15:35 ` [dts] [dts 2/5] test_plans/pmd_test_plan:update " lingwei
2020-09-07 15:35 ` [dts] [dts 3/5] test_plans/vmdq_test_plan:update " lingwei
2020-09-07 15:35 ` [dts] [dts 4/5] test_plans/ptpclient_test_plan:update " lingwei
2020-09-07 15:35 ` [dts] [dts 5/5] test_plans/vf_l3fwd_test_plan:update " lingwei
2020-09-07  8:21   ` Ma, LihongX
2020-09-07 16:49 [dts] [PATCH V3 0/5] update " lingwei
2020-09-07 16:49 ` [dts] [dts 1/5] test_plans/nic_single_core_perf_test_plan:update " lingwei

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