From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 14406A0350; Wed, 19 Jan 2022 03:52:17 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D46E24068A; Wed, 19 Jan 2022 03:52:16 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 1B3314013F for ; Wed, 19 Jan 2022 03:52:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1642560735; x=1674096735; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=DVa4H6om43TkfHAGK3G2OQaNBCna3du7U8Hb+/cSI5c=; b=SxFKzhlGguX5jLGzcKq2qR2q7Zcza8HMX4Z9pQdYLxtmtgf5DFNUg6Up cbHwSgLqvoiA9UjOEYL3GsIDSSpgyG4qEsmU0H7+fir2KMh3OgF2bQEjO LDOeA5LpQFAwp+sAUhlHoAOAJTkeGY54gYp8Ce2ErUL3YozsxM2JroNOB bDOqIa4jvbvZzuM2uEGQbUYh3eAYfX61srYj5rxnTthuA5JHce2lEqKhx YJDk+uHqA5VqPAEhqG0Rw9uPntcEpCcstJGcd2iE3K4RH/U7611/iTHSx H+BgPXwtZA4LnUcpnFJBlh6myES68soAvBN2jk1y6hCLvz3+/lrIUAkF3 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10231"; a="225642164" X-IronPort-AV: E=Sophos;i="5.88,298,1635231600"; d="scan'208";a="225642164" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Jan 2022 18:52:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,298,1635231600"; d="scan'208";a="474979162" Received: from dpdk-qifu-cxl.sh.intel.com ([10.67.118.191]) by orsmga003.jf.intel.com with ESMTP; 18 Jan 2022 18:51:59 -0800 From: Qi Fu To: dts@dpdk.org Cc: Qi Fu Subject: [dts][PATCH V3]test_plans: add test plan for cvl 1pps signal Date: Wed, 19 Jan 2022 19:22:35 +0800 Message-Id: <20220119112235.878680-1-qi.fu@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dts-bounces@dpdk.org Add test plan for cvl enable 1PPS signal. Signed-off-by: Qi Fu --- test_plans/cvl_1pps_signal_test_plan.rst | 160 +++++++++++++++++++++++ test_plans/index.rst | 1 + 2 files changed, 161 insertions(+) create mode 100644 test_plans/cvl_1pps_signal_test_plan.rst diff --git a/test_plans/cvl_1pps_signal_test_plan.rst b/test_plans/cvl_1pps= _signal_test_plan.rst new file mode 100644 index 00000000..8d279ff7 --- /dev/null +++ b/test_plans/cvl_1pps_signal_test_plan.rst @@ -0,0 +1,160 @@ +.. Copyright (c) <2021>, Intel Corporation=0D + All rights reserved.=0D +=0D + Redistribution and use in source and binary forms, with or without=0D + modification, are permitted provided that the following conditions=0D + are met:=0D +=0D + - Redistributions of source code must retain the above copyright=0D + notice, this list of conditions and the following disclaimer.=0D +=0D + - Redistributions in binary form must reproduce the above copyright=0D + notice, this list of conditions and the following disclaimer in=0D + the documentation and/or other materials provided with the=0D + distribution.=0D +=0D + - Neither the name of Intel Corporation nor the names of its=0D + contributors may be used to endorse or promote products derived=0D + from this software without specific prior written permission.=0D +=0D + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS=0D + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT=0D + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS=0D + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE=0D + COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,=0D + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES=0D + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR=0D + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)=0D + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,=0D + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)=0D + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED=0D + OF THE POSSIBILITY OF SUCH DAMAGE.=0D +=0D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=0D +CVL 1PPS Signal Test Plan=0D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=0D +=0D +Description=0D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0D +The E810 supports a total of four single-ended GPIO signals(SPD[20:23])plu= s one different GPIO signal (CLK_OUT_P/N),=0D +which is configured by default 1PPS(out). The SPD[20:23] is mapping to pin= _id[0:3].=0D +This test plan is designed to check the value of related registers, which = make up the 1PPS signal.=0D +The registers address depends on some hardware config.=0D +The test cases only give the example of Columbiaville_25g and Columbiavill= e_100g.=0D +=0D +=0D +Prerequisites=0D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0D +=0D +Topology=0D +--------=0D +DUT port 0 <----> Tester port 0=0D +=0D +Hardware=0D +--------=0D +Supported NICs: columbiaville_25g/columbiaville_100g=0D +=0D +Software=0D +--------=0D +dpdk: http://dpdk.org/git/dpdk=0D +scapy: http://www.secdev.org/projects/scapy/=0D +=0D +General set up=0D +--------------=0D +1. Compile DPDK::=0D +=0D + # CC=3Dgcc meson --werror -Denable_kmods=3DTrue -Dlibdir=3Dlib --defau= lt-library=3Dstatic =0D + # ninja -C -j 110=0D +=0D +2. Get the pci device id and interface of DUT and tester.=0D + For example, 0000:18:00.0 and 0000:18:00.1 is pci device id,=0D + ens785f0 and ens785f1 is interface::=0D +=0D + # ./usertools/dpdk-devbind.py -s=0D +=0D + 0000:18:00.0 'Device 159b' if=3Dens785f0 drv=3Dice unused=3Dvfio-pci=0D + 0000:18:00.1 'Device 159b' if=3Dens785f1 drv=3Dice unused=3Dvfio-pci=0D +=0D +3. Bind the DUT port to dpdk::=0D +=0D + # ./usertools/dpdk-devbind.py -b vfio-pci =0D +=0D +=0D +Test case=0D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=0D +=0D +Test case 1: check registers when pin id is 0=0D +---------------------------------------------=0D +=0D +this case is designed to check the register value is right when pin id is = 0.=0D +=0D +test steps=0D +~~~~~~~~~~=0D +1. start testpmd with different pin_id and dump registers::=0D +=0D + /app/dpdk-testpmd -a ,pps_out=3D'[pin:0]' -- -i --rxq=3D4 --txq=3D4=0D + testpmd> read reg 0 0x00088998=0D + testpmd> read reg 0 0x000889B8=0D + testpmd> read reg 0 0x00088928=0D + testpmd> read reg 0 0x00088930=0D + testpmd> read reg 0 0x000880C8=0D +=0D +2. check the GLTSYN_AUX_OUT_0[0] 0x00088998 is 0x00000007 (7), GLTSYN_CLKO= _0[0] 0x000889B8 is 0x1DCD6500 (500000000), the 0x00088928 and 0x00088930 i= s non-zero,=0D + GLGEN_GPIO_CTL[0][2] 0x000880C8 is 8, the 4th bit is 1=0D +=0D +Test case 2: check registers when pin id is 1=0D +---------------------------------------------=0D +=0D +this case is designed to check the register value is right when pin id is = 1.=0D +=0D +test steps=0D +~~~~~~~~~~=0D +1. start testpmd with different pin_id and dump registers::=0D +=0D + ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:0= 0.0,pps_out=3D'[pin:1]' -- -i --rxq=3D4 --txq=3D4=0D + testpmd> read reg 0 0x000889A0=0D + testpmd> read reg 0 0x000889C0=0D + testpmd> read reg 0 0x00088938=0D + testpmd> read reg 0 0x00088940=0D + testpmd> read reg 0 0x000880CC=0D +=0D +2. check the GLTSYN_AUX_OUT_1[0] 0x000889A0 is 0x00000007 (7), GLTSYN_CLKO= _1[0] 0x000889C0 is 0x1DCD6500 (500000000), the 0x00088938 and 0x00088940 i= s non-zero,=0D + GLGEN_GPIO_CTL[1][2] 0x000880CC is 9, the 4th bit is 1=0D +=0D +Test case 3: check registers when pin id is 2=0D +---------------------------------------------=0D +=0D +this case is designed to check the register value is right when pin id is = 2.=0D +=0D +test steps=0D +~~~~~~~~~~=0D +1. start testpmd with different pin_id and dump registers::=0D +=0D + ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:0= 0.0,pps_out=3D'[pin:2]' -- -i --rxq=3D4 --txq=3D4=0D + testpmd> read reg 0 0x000889A8=0D + testpmd> read reg 0 0x000889C8=0D + testpmd> read reg 0 0x00088948=0D + testpmd> read reg 0 0x00088950=0D + testpmd> read reg 0 0x000880D0=0D +=0D +2. check the GLTSYN_AUX_OUT_2[0] 0x000889A8 is 0x00000007 (7), GLTSYN_CLKO= _2[0] 0x000889C8 is 0x1DCD6500 (500000000), the 0x00088948 and 0x00088950 i= s non-zero,=0D + GLGEN_GPIO_CTL[2][2] 0x000880D0 is A, the 4th bit is 1=0D +=0D +Test case 4: check registers when pin id is 3=0D +---------------------------------------------=0D +=0D +this case is designed to check the register value is right when pin id is = 3.=0D +=0D +test steps=0D +~~~~~~~~~~=0D +1. start testpmd with different pin_id and dump registers::=0D +=0D + ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:0= 0.0,pps_out=3D'[pin:3]' -- -i --rxq=3D4 --txq=3D4=0D + testpmd> read reg 0 0x000889B0=0D + testpmd> read reg 0 0x000889D0=0D + testpmd> read reg 0 0x00088958=0D + testpmd> read reg 0 0x00088960=0D + testpmd> read reg 0 0x000880D4=0D +=0D +2. check the GLTSYN_AUX_OUT_3[0] 0x000889B0 is 0x00000007 (7), GLTSYN_CLKO= _3[0] 0x000889D0 is 0x1DCD6500 (500000000), the 0x00088958 and 0x00088960 i= s non-zero,=0D + GLGEN_GPIO_CTL[3][2] 0x000880D4 is B, the 4th bit is 1 \ No newline at end of file diff --git a/test_plans/index.rst b/test_plans/index.rst index 68250fca..f83bacfe 100644 --- a/test_plans/index.rst +++ b/test_plans/index.rst @@ -69,6 +69,7 @@ The following are the test plans for the DPDK DTS automat= ed test system. cvl_switch_filter_test_plan cvl_switch_filter_pppoe_test_plan cvl_vf_support_multicast_address_test_plan + cvl_1pps_signal_test_plan cloud_filter_with_l4_port_test_plan dcf_lifecycle_test_plan crypto_perf_cryptodev_perf_test_plan --=20 2.25.1