From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D9EF4A04AD; Tue, 8 Feb 2022 10:12:38 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A8F51410FD; Tue, 8 Feb 2022 10:12:38 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 71A13410FC for ; Tue, 8 Feb 2022 10:12:36 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644311556; x=1675847556; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=ikxB64QWA4z/vRHG2oRBdcSZETjyEj5vky/BkzT/GPM=; b=Q2cythto1j6Dmo1rVEeEJXXge/u+abR6iuZud4l9OxRJOFh5IhuNsOqI ruSHZOZd7Iz1typU/XokHO4m2aojN8+rOwQ2HFO2gacOheh3vII3v0Yke DWkslslHj5MVNe+kzPTkAYDrFd1mNHAgcCv6UOjp9w3RZKLiSUjZEaju+ wBgB2220oXbNBf6ByxL1WbkKYJmgPCuYsyP4zwjRO1SyajYHkfxNC1C0q b4ysc19/j3N1zLJDWigNgIEIB/VZzBn8fONNXskSnZyzwVoQECF8L8vTe 86suHhItg0fs0aqnHgxkVhENAkGEJYi4loSIM+jnHgRzE33fCBlONFRkl A==; X-IronPort-AV: E=McAfee;i="6200,9189,10251"; a="246496573" X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="246496573" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 01:12:35 -0800 X-IronPort-AV: E=Sophos;i="5.88,352,1635231600"; d="scan'208";a="678044114" Received: from unknown (HELO localhost.localdomain) ([10.239.251.247]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2022 01:12:33 -0800 From: Peng Zhang To: dts@dpdk.org Cc: qi.fu@intel.com, Peng Zhang Subject: [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4 new cases Date: Tue, 8 Feb 2022 17:15:34 +0800 Message-Id: <20220208091534.331932-1-peng1x.zhang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dts-bounces@dpdk.org Update script of 4 new cases according to comments and v5 test plan. Signed-off-by: Peng Zhang --- tests/TestSuite_cvl_1pps_signal.py | 131 +++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100755 tests/TestSuite_cvl_1pps_signal.py diff --git a/tests/TestSuite_cvl_1pps_signal.py b/tests/TestSuite_cvl_1pps_signal.py new file mode 100755 index 00000000..4304ad64 --- /dev/null +++ b/tests/TestSuite_cvl_1pps_signal.py @@ -0,0 +1,131 @@ +# BSD LICENSE +# +# Copyright(c) 2010-2022 Intel Corporation. All rights reserved. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Intel Corporation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +import re +from framework.pmd_output import PmdOutput +from framework.test_case import TestCase, check_supported_nic + + +class TestCVL1PPS(TestCase): + supported_nic = ['columbiaville_100g', 'columbiaville_25g'] + @check_supported_nic(supported_nic) + def set_up_all(self): + """ + Run at the start of each test suite. + prerequisites. + """ + # Based on h/w type, chose how many ports to use + dut_ports = self.dut.get_ports(self.nic) + self.verify(len(dut_ports) >= 1, "Insufficient ports for testing") + # Verify that enough threads are available + self.cores = self.dut.get_core_list("1S/2C/1T") + self.verify(self.cores, "Insufficient cores for speed testing") + self.pci = self.dut.ports_info[dut_ports[0]]['pci'] + self.pmd_output = PmdOutput(self.dut) + self.GLTSYN_AUX = re.compile(r'0x00000007\s+\(7\)') + self.GLTSYN_CLKO = re.compile(r'0x1DCD6500\s+\(500000000\)') + self.pattern = re.compile('register\s+at\s+offset\s+.*:\s+(?P0x\w+)\s+\(\d+\)') + + def set_up(self): + """ + Run before each test case. + """ + pass + + def read_register(self, addr, port_id=0): + cmd = 'read reg {} {}'.format(port_id, addr) + return self.pmd_output.execute_cmd(cmd) + + def launch_testpmd(self, pin_id, rxq=4, txq=4): + self.out = self.pmd_output.start_testpmd(cores="1S/2C/1T", param="--rxq={} --txq={} ".format(rxq, txq), + eal_param="-a {},pps_out='[pin:{}]'".format(self.pci, pin_id)) + # Check the GLTSYN_AUX_OUT, GLTSYN_CLKO and other two registers + def check_four_registers(self, pin_id, addrs, port_id=0): + self.launch_testpmd(pin_id) + for i in range(len(addrs)): + out = self.read_register(addrs[i], port_id=port_id) + if i == 0: + pattern = self.GLTSYN_AUX + elif i == 1: + pattern = self.GLTSYN_CLKO + else: + pattern = self.pattern + res = pattern.search(out) + self.verify(res, 'pattern:{} not found in output info: {}'.format(pattern, out)) + if i > 1: + actual_value = int(res.group('hex'), 16) + self.verify(actual_value != 0, + 'check pin id:{0} register address:{1} failed, expected value is non-zero, actual value is:{2}'.format(pin_id,addrs[i],actual_value)) + self.logger.info('check pin id: {0} register address: {1} pass'.format(pin_id,addrs[i])) + # complete checking registers + self.quit_testpmd() + return res + + def check_GLGEN_GPIO_CTL_value(self, hex_value, target_value): + self.verify(hex_value[-3] == target_value, + 'check register failed, target value is {} not match expected value {}'.format(hex_value[-3], target_value)) + bit_5th = bin(int(hex_value, 16))[-5] + self.verify(bit_5th == '1', 'check register failed, the 5th bit is {} not match expected value {}'.format(bit_5th, 1)) + self.logger.info('check register value {} pass'.format(hex_value)) + + def test_check_register_with_pin_id_0(self): + addrs = ['0x00088998', '0x000889B8', '0x00088928', '0x00088930', '0x000880C8'] + res = self.check_four_registers(pin_id=0, addrs=addrs) + # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[0] 0x000880C8 is 8. And the 5th binary digit is 1. + self.check_GLGEN_GPIO_CTL_value(hex_value=res.group('hex'), target_value='8') + + def test_check_register_with_pin_id_1(self): + addrs = ['0x000889A0', '0x000889C0', '0x00088938', '0x00088940', '0x000880CC'] + res = self.check_four_registers(pin_id=1, addrs=addrs) + # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[1] 0x000880CC is 9. And the 5th binary digit is 1. + self.check_GLGEN_GPIO_CTL_value(hex_value=res.group('hex'), target_value='9') + + def test_check_register_with_pin_id_2(self): + addrs = ['0x000889A8', '0x000889C8', '0x00088948', '0x00088950', '0x000880D0'] + res = self.check_four_registers(pin_id=2, addrs=addrs) + # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[2] 0x000880D0 is A. And the 5th binary digit is 1. + self.check_GLGEN_GPIO_CTL_value(hex_value=res.group('hex'), target_value='A') + + def test_check_register_with_pin_id_3(self): + addrs = ['0x000889B0', '0x000889D0', '0x00088958', '0x00088960', '0x000880D4'] + res = self.check_four_registers(pin_id=3, addrs=addrs) + # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[3] 0x000880D4 is B. And the 5th binary digit is 1. + self.check_GLGEN_GPIO_CTL_value(hex_value=res.group('hex'), target_value='B') + + def quit_testpmd(self): + self.pmd_output.quit() + + def tear_down(self): + self.dut.kill_all() + + def tear_down_all(self): + self.dut.kill_all() -- 2.17.1