* [dts][PATCH V1 5/5] test_plans/index: add new testsuite
@ 2022-04-06 8:58 Wei Ling
0 siblings, 0 replies; 8+ messages in thread
From: Wei Ling @ 2022-04-06 8:58 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
As commit 53d3f4778c(vhost: integrate dmadev in asynchronous data-path),
add vm2vm_virtio_user_cbdma new testplan into index.rst.
Signed-off-by: Wei Ling <weix.ling@intel.com>
---
test_plans/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/test_plans/index.rst b/test_plans/index.rst
index f8118d14..3f0fba32 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -230,6 +230,7 @@ The following are the test plans for the DPDK DTS automated test system.
virtio_smoke_test_plan
vm2vm_virtio_net_perf_test_plan
vm2vm_virtio_pmd_test_plan
+ vm2vm_virtio_pmd_cbdma_test_plan
dpdk_gro_lib_test_plan
dpdk_gso_lib_test_plan
vswitch_sample_cbdma_test_plan
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [dts][PATCH V1 5/5] test_plans/index: add new testsuite
@ 2022-04-15 3:26 Wei Ling
2022-04-22 6:01 ` Huang, ChenyuX
0 siblings, 1 reply; 8+ messages in thread
From: Wei Ling @ 2022-04-15 3:26 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
As commit 53d3f4778c(vhost: integrate dmadev in asynchronous data-path),
add loopback_virtio_user_server_mode_cbdma_test_plan new testplan into index.rst.
Signed-off-by: Wei Ling <weix.ling@intel.com>
---
test_plans/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/test_plans/index.rst b/test_plans/index.rst
index f8118d14..a6a396c7 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -121,6 +121,7 @@ The following are the test plans for the DPDK DTS automated test system.
linux_modules_test_plan
loopback_multi_paths_port_restart_test_plan
loopback_virtio_user_server_mode_test_plan
+ loopback_virtio_user_server_mode_cbdma_test_plan
mac_filter_test_plan
macsec_for_ixgbe_test_plan
metering_and_policing_test_plan
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* RE: [dts][PATCH V1 5/5] test_plans/index: add new testsuite
2022-04-15 3:26 Wei Ling
@ 2022-04-22 6:01 ` Huang, ChenyuX
0 siblings, 0 replies; 8+ messages in thread
From: Huang, ChenyuX @ 2022-04-22 6:01 UTC (permalink / raw)
To: Ling, WeiX, dts; +Cc: Ling, WeiX
> -----Original Message-----
> From: Wei Ling <weix.ling@intel.com>
> Sent: Friday, April 15, 2022 11:26 AM
> To: dts@dpdk.org
> Cc: Ling, WeiX <weix.ling@intel.com>
> Subject: [dts][PATCH V1 5/5] test_plans/index: add new testsuite
Tested-by: Chenyu Huang <chenyux.huang@intel.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [dts][PATCH V1 5/5] test_plans/index: add new testsuite
@ 2022-04-06 9:10 Wei Ling
2022-04-22 6:01 ` Huang, ChenyuX
0 siblings, 1 reply; 8+ messages in thread
From: Wei Ling @ 2022-04-06 9:10 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
As commit 53d3f4778c(vhost: integrate dmadev in asynchronous data-path),
add vm2vm_virtio_net_perf_cbdma new testplan into index.rst.
Signed-off-by: Wei Ling <weix.ling@intel.com>
---
test_plans/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/test_plans/index.rst b/test_plans/index.rst
index f8118d14..ff8cba5d 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -229,6 +229,7 @@ The following are the test plans for the DPDK DTS automated test system.
virtio_perf_cryptodev_func_test_plan
virtio_smoke_test_plan
vm2vm_virtio_net_perf_test_plan
+ vm2vm_virtio_net_perf_cbdma_test_plan
vm2vm_virtio_pmd_test_plan
dpdk_gro_lib_test_plan
dpdk_gso_lib_test_plan
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* RE: [dts][PATCH V1 5/5] test_plans/index: add new testsuite
2022-04-06 9:10 Wei Ling
@ 2022-04-22 6:01 ` Huang, ChenyuX
0 siblings, 0 replies; 8+ messages in thread
From: Huang, ChenyuX @ 2022-04-22 6:01 UTC (permalink / raw)
To: Ling, WeiX, dts; +Cc: Ling, WeiX
> -----Original Message-----
> From: Wei Ling <weix.ling@intel.com>
> Sent: Wednesday, April 6, 2022 5:11 PM
> To: dts@dpdk.org
> Cc: Ling, WeiX <weix.ling@intel.com>
> Subject: [dts][PATCH V1 5/5] test_plans/index: add new testsuite
Tested-by: Chenyu Huang <chenyux.huang@intel.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [dts][PATCH V1 5/5] test_plans/index: add new testsuite
@ 2022-04-06 8:22 Wei Ling
0 siblings, 0 replies; 8+ messages in thread
From: Wei Ling @ 2022-04-06 8:22 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
As commit 53d3f4778c(vhost: integrate dmadev in asynchronous data-path),
add vm2vm_virtio_net_perf_cbdma new testplan into index.rst.
Signed-off-by: Wei Ling <weix.ling@intel.com>
---
test_plans/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/test_plans/index.rst b/test_plans/index.rst
index f8118d14..ff8cba5d 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -229,6 +229,7 @@ The following are the test plans for the DPDK DTS automated test system.
virtio_perf_cryptodev_func_test_plan
virtio_smoke_test_plan
vm2vm_virtio_net_perf_test_plan
+ vm2vm_virtio_net_perf_cbdma_test_plan
vm2vm_virtio_pmd_test_plan
dpdk_gro_lib_test_plan
dpdk_gso_lib_test_plan
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [dts][PATCH V1 5/5] test_plans/index: add new testsuite
@ 2022-04-06 2:49 Wei Ling
0 siblings, 0 replies; 8+ messages in thread
From: Wei Ling @ 2022-04-06 2:49 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
As commit 53d3f4778c(vhost: integrate dmadev in asynchronous data-path),
add vm2vm_virtio_user_cbdma new testplan into index.rst.
Signed-off-by: Wei Ling <weix.ling@intel.com>
---
test_plans/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/test_plans/index.rst b/test_plans/index.rst
index f8118d14..3f0fba32 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -230,6 +230,7 @@ The following are the test plans for the DPDK DTS automated test system.
virtio_smoke_test_plan
vm2vm_virtio_net_perf_test_plan
vm2vm_virtio_pmd_test_plan
+ vm2vm_virtio_pmd_cbdma_test_plan
dpdk_gro_lib_test_plan
dpdk_gso_lib_test_plan
vswitch_sample_cbdma_test_plan
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [dts][PATCH V1 5/5] test_plans/index: add new testsuite
@ 2022-04-02 6:34 Wei Ling
0 siblings, 0 replies; 8+ messages in thread
From: Wei Ling @ 2022-04-02 6:34 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
As commit 53d3f4778c(vhost: integrate dmadev in asynchronous data-path),
add vm2vm_virtio_user_cbdma new testplan into index.rst.
Signed-off-by: Wei Ling <weix.ling@intel.com>
---
test_plans/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/test_plans/index.rst b/test_plans/index.rst
index f8118d14..05794f98 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -297,6 +297,7 @@ The following are the test plans for the DPDK DTS automated test system.
port_control_test_plan
port_representor_test_plan
vm2vm_virtio_user_test_plan
+ vm2vm_virtio_user_cbdma_test_plan
vmdq_dcb_test_plan
acl_test_plan
power_negative_test_plan
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-04-22 6:02 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2022-04-15 3:26 Wei Ling
2022-04-22 6:01 ` Huang, ChenyuX
2022-04-06 9:10 Wei Ling
2022-04-22 6:01 ` Huang, ChenyuX
2022-04-06 8:22 Wei Ling
2022-04-06 2:49 Wei Ling
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