* [dts][PATCH V1 1/5] test_plans/index: add new testsuite
@ 2022-04-21 7:57 Wei Ling
0 siblings, 0 replies; 2+ messages in thread
From: Wei Ling @ 2022-04-21 7:57 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
As commit 53d3f4778c(vhost: integrate dmadev in asynchronous data-path),
add vm2vm_virtio_user_cbdma_test_plan into test_plans/index.rst.
Signed-off-by: Wei Ling <weix.ling@intel.com>
---
test_plans/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/test_plans/index.rst b/test_plans/index.rst
index f8118d14..3f0fba32 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -230,6 +230,7 @@ The following are the test plans for the DPDK DTS automated test system.
virtio_smoke_test_plan
vm2vm_virtio_net_perf_test_plan
vm2vm_virtio_pmd_test_plan
+ vm2vm_virtio_pmd_cbdma_test_plan
dpdk_gro_lib_test_plan
dpdk_gso_lib_test_plan
vswitch_sample_cbdma_test_plan
--
2.25.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* [dts][PATCH V1 1/5] test_plans/index: add new testsuite
@ 2022-04-21 7:02 Wei Ling
0 siblings, 0 replies; 2+ messages in thread
From: Wei Ling @ 2022-04-21 7:02 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
As commit 53d3f4778c(vhost: integrate dmadev in asynchronous data-path),
add vm2vm_virtio_user_cbdma_test_plan into test_plans/index.rst.
Signed-off-by: Wei Ling <weix.ling@intel.com>
---
test_plans/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/test_plans/index.rst b/test_plans/index.rst
index f8118d14..05794f98 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -297,6 +297,7 @@ The following are the test plans for the DPDK DTS automated test system.
port_control_test_plan
port_representor_test_plan
vm2vm_virtio_user_test_plan
+ vm2vm_virtio_user_cbdma_test_plan
vmdq_dcb_test_plan
acl_test_plan
power_negative_test_plan
--
2.25.1
^ permalink raw reply [flat|nested] 2+ messages in thread
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