From: Yu Jiang <yux.jiang@intel.com>
To: lijuan.tu@intel.com, dts@dpdk.org
Cc: Yu Jiang <yux.jiang@intel.com>
Subject: [dts][PATCH V1 0/2] l3fwdacl: merge l3fwd-acl with l3fwd
Date: Wed, 15 Jun 2022 12:48:19 +0000 [thread overview]
Message-ID: <20220615124821.1582235-1-yux.jiang@intel.com> (raw)
l3fwdacl: merge l3fwd-acl with l3fwd
Yu Jiang (2):
test_plans/l3fwdacl: merge l3fwd-acl wtih l3fwd
tests/l3fwdacl: merge l3fwd-acl with l3fwd and fix to support
different force-max-simd-bitwidth
conf/app_name.cfg | 3 +-
test_plans/l3fwdacl_test_plan.rst | 69 +++++++++++++++++++++----------
tests/TestSuite_l3fwdacl.py | 49 +++++++++++++---------
3 files changed, 77 insertions(+), 44 deletions(-)
--
2.25.1
next reply other threads:[~2022-06-15 4:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-15 12:48 Yu Jiang [this message]
2022-06-15 12:48 ` [dts][PATCH V1 1/2] test_plans/l3fwdacl: " Yu Jiang
2022-06-15 12:48 ` [dts][PATCH V1 2/2] tests/l3fwdacl: merge l3fwd-acl with l3fwd and fix to support different force-max-simd-bitwidth Yu Jiang
2022-06-15 8:52 ` Chen, LingliX
2022-06-15 9:07 ` lijuan.tu
2022-06-21 7:13 ` lijuan.tu
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