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* [dts][PATCH V1] tests/ice_1pps_signal: remove suite and test plan due to dpdk22.11 changes
@ 2022-12-29  6:35 Yu Jiang
  2023-01-03  5:45 ` Fu, Qi
  0 siblings, 1 reply; 5+ messages in thread
From: Yu Jiang @ 2022-12-29  6:35 UTC (permalink / raw)
  To: qi.fu, dts; +Cc: Yu Jiang

According to dpdk22.11 commit 1bcb7ba9 ("app/testpmd: drop PCI register commands"),
reading and setting port registers related cmds have been removded from dpdk. 

Signed-off-by: Yu Jiang <yux.jiang@intel.com>
---
 test_plans/ice_1pps_signal_test_plan.rst | 131 -----------------------
 test_plans/index.rst                     |   1 -
 tests/TestSuite_ice_1pps_signal.py       | 128 ----------------------
 3 files changed, 260 deletions(-)
 delete mode 100644 test_plans/ice_1pps_signal_test_plan.rst
 delete mode 100644 tests/TestSuite_ice_1pps_signal.py

diff --git a/test_plans/ice_1pps_signal_test_plan.rst b/test_plans/ice_1pps_signal_test_plan.rst
deleted file mode 100644
index 1c7c4d8a..00000000
--- a/test_plans/ice_1pps_signal_test_plan.rst
+++ /dev/null
@@ -1,131 +0,0 @@
-.. SPDX-License-Identifier: BSD-3-Clause
-   Copyright(c) 2021 Intel Corporation
-
-=========================
-ICE 1PPS Signal Test Plan
-=========================
-
-Description
-===========
-The Intel® Ethernet 800 Series supports a total of four single-ended GPIO signals(SPD[20:23])plus
-one different GPIO signal (CLK_OUT_P/N), which is configured by default 1PPS(out). The SPD[20:23]
-is mapping to pin_id[0:3]. This test plan is designed to check the value of related registers,
-which make up the 1PPS signal. The registers address depends on some hardware config.
-The test cases only give the example of E810-XXVDA4 and E810-CQ.
-
-
-Prerequisites
-=============
-
-Topology
---------
-DUT port 0 <----> Tester port 0
-
-Hardware
---------
-Supported NICs: Intel® Ethernet 800 Series E810-XXVDA4/E810-CQ
-
-Software
---------
-dpdk: http://dpdk.org/git/dpdk
-scapy: http://www.secdev.org/projects/scapy/
-
-General set up
---------------
-1. Compile DPDK::
-
-    # CC=gcc meson --werror -Denable_kmods=True -Dlibdir=lib --default-library=static <dpdk build dir>
-    # ninja -C <dpdk build dir> -j 110
-
-2. Get the pci device id and interface of DUT and tester.
-   For example, 0000:18:00.0 and 0000:18:00.1 is pci device id,
-   ens785f0 and ens785f1 is interface::
-
-    <dpdk dir># ./usertools/dpdk-devbind.py -s
-
-    0000:18:00.0 'Device 159b' if=ens785f0 drv=ice unused=vfio-pci
-    0000:18:00.1 'Device 159b' if=ens785f1 drv=ice unused=vfio-pci
-
-3. Bind the DUT port to dpdk::
-
-    <dpdk dir># ./usertools/dpdk-devbind.py -b vfio-pci <DUT port pci device id>
-
-
-Test case
-=========
-
-Test case 1: check registers when pin id is 0
----------------------------------------------
-
-this case is designed to check the register value is right when pin id is 0.
-
-test steps
-~~~~~~~~~~
-1. start testpmd with different pin_id and dump registers::
-
-    <dpdk build dir>/app/dpdk-testpmd <EAL options> -a <DUT port pci device id>,pps_out='[pin:0]' -- -i --rxq=4 --txq=4
-    testpmd> read reg 0 0x00088998
-    testpmd> read reg 0 0x000889B8
-    testpmd> read reg 0 0x00088928
-    testpmd> read reg 0 0x00088930
-    testpmd> read reg 0 0x000880C8
-
-2. check the GLTSYN_AUX_OUT_0[0] 0x00088998 is 0x00000007 (7), GLTSYN_CLKO_0[0] 0x000889B8 is 0x1DCD6500 (500000000), the 0x00088928 and 0x00088930 is non-zero,
-   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[0] 0x000880C8 is 8. And the 5th binary digit is 1.
-
-Test case 2: check registers when pin id is 1
----------------------------------------------
-
-this case is designed to check the register value is right when pin id is 1.
-
-test steps
-~~~~~~~~~~
-1. start testpmd with different pin_id and dump registers::
-
-    ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:1]' -- -i --rxq=4 --txq=4
-    testpmd> read reg 0 0x000889A0
-    testpmd> read reg 0 0x000889C0
-    testpmd> read reg 0 0x00088938
-    testpmd> read reg 0 0x00088940
-    testpmd> read reg 0 0x000880CC
-
-2. check the GLTSYN_AUX_OUT_1[0] 0x000889A0 is 0x00000007 (7), GLTSYN_CLKO_1[0] 0x000889C0 is 0x1DCD6500 (500000000), the 0x00088938 and 0x00088940 is non-zero,
-   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[1] 0x000880CC is 9. And the 5th binary digit is 1.
-
-Test case 3: check registers when pin id is 2
----------------------------------------------
-
-this case is designed to check the register value is right when pin id is 2.
-
-test steps
-~~~~~~~~~~
-1. start testpmd with different pin_id and dump registers::
-
-    ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:2]' -- -i --rxq=4 --txq=4
-    testpmd> read reg 0 0x000889A8
-    testpmd> read reg 0 0x000889C8
-    testpmd> read reg 0 0x00088948
-    testpmd> read reg 0 0x00088950
-    testpmd> read reg 0 0x000880D0
-
-2. check the GLTSYN_AUX_OUT_2[0] 0x000889A8 is 0x00000007 (7), GLTSYN_CLKO_2[0] 0x000889C8 is 0x1DCD6500 (500000000), the 0x00088948 and 0x00088950 is non-zero,
-   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[2] 0x000880D0 is A. And the 5th binary digit is 1.
-
-Test case 4: check registers when pin id is 3
----------------------------------------------
-
-this case is designed to check the register value is right when pin id is 3.
-
-test steps
-~~~~~~~~~~
-1. start testpmd with different pin_id and dump registers::
-
-    ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:3]' -- -i --rxq=4 --txq=4
-    testpmd> read reg 0 0x000889B0
-    testpmd> read reg 0 0x000889D0
-    testpmd> read reg 0 0x00088958
-    testpmd> read reg 0 0x00088960
-    testpmd> read reg 0 0x000880D4
-
-2. check the GLTSYN_AUX_OUT_3[0] 0x000889B0 is 0x00000007 (7), GLTSYN_CLKO_3[0] 0x000889D0 is 0x1DCD6500 (500000000), the 0x00088958 and 0x00088960 is non-zero,
-   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[3] 0x000880D4 is B. And the 5th binary digit is 1.
\ No newline at end of file
diff --git a/test_plans/index.rst b/test_plans/index.rst
index 9ca954e2..d2552f22 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -54,7 +54,6 @@ The following are the test plans for the DPDK DTS automated test system.
     ice_switch_filter_test_plan
     ice_switch_filter_pppoe_test_plan
     ice_vf_support_multicast_address_test_plan
-    ice_1pps_signal_test_plan
     ice_rss_protocol_agnostic_flow_test_plan
     ice_fdir_protocol_agnostic_flow_test_plan
     cloud_filter_with_l4_port_test_plan
diff --git a/tests/TestSuite_ice_1pps_signal.py b/tests/TestSuite_ice_1pps_signal.py
deleted file mode 100644
index ef94d466..00000000
--- a/tests/TestSuite_ice_1pps_signal.py
+++ /dev/null
@@ -1,128 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2010-2022 Intel Corporation
-#
-
-import re
-
-from framework.pmd_output import PmdOutput
-from framework.test_case import TestCase, check_supported_nic
-
-
-class TestICE1PPS(TestCase):
-    supported_nic = ["ICE_100G-E810C_QSFP", "ICE_25G-E810C_SFP", "ICE_25G-E810_XXV_SFP"]
-
-    @check_supported_nic(supported_nic)
-    def set_up_all(self):
-        """
-        Run at the start of each test suite.
-        prerequisites.
-        """
-        # Based on h/w type, chose how many ports to use
-        dut_ports = self.dut.get_ports(self.nic)
-        self.verify(len(dut_ports) >= 1, "Insufficient ports for testing")
-        # Verify that enough threads are available
-        self.cores = self.dut.get_core_list("1S/2C/1T")
-        self.verify(self.cores, "Insufficient cores for speed testing")
-        self.pci = self.dut.ports_info[dut_ports[0]]["pci"]
-        self.pmd_output = PmdOutput(self.dut)
-        self.GLTSYN_AUX = re.compile(r"0x00000007\s+\(7\)")
-        self.GLTSYN_CLKO = re.compile(r"0x1DCD6500\s+\(500000000\)")
-        self.pattern = re.compile(
-            "register\s+at\s+offset\s+.*:\s+(?P<hex>0x\w+)\s+\(\d+\)"
-        )
-
-    def set_up(self):
-        """
-        Run before each test case.
-        """
-        pass
-
-    def read_register(self, addr, port_id=0):
-        cmd = "read reg {} {}".format(port_id, addr)
-        return self.pmd_output.execute_cmd(cmd)
-
-    def launch_testpmd(self, pin_id, rxq=4, txq=4):
-        self.out = self.pmd_output.start_testpmd(
-            cores="1S/2C/1T",
-            param="--rxq={} --txq={} ".format(rxq, txq),
-            eal_param="-a {},pps_out='[pin:{}]'".format(self.pci, pin_id),
-        )
-        # Check the GLTSYN_AUX_OUT, GLTSYN_CLKO and other two registers
-
-    def check_four_registers(self, pin_id, addrs, port_id=0):
-        self.launch_testpmd(pin_id)
-        for i in range(len(addrs)):
-            out = self.read_register(addrs[i], port_id=port_id)
-            if i == 0:
-                pattern = self.GLTSYN_AUX
-            elif i == 1:
-                pattern = self.GLTSYN_CLKO
-            else:
-                pattern = self.pattern
-            res = pattern.search(out)
-            self.verify(
-                res, "pattern:{} not found in output info: {}".format(pattern, out)
-            )
-            if i > 1:
-                actual_value = int(res.group("hex"), 16)
-                self.verify(
-                    actual_value != 0,
-                    "check pin id:{0} register address:{1} failed, expected value is non-zero, actual value is:{2}".format(
-                        pin_id, addrs[i], actual_value
-                    ),
-                )
-            self.logger.info(
-                "check pin id: {0} register address: {1} pass".format(pin_id, addrs[i])
-            )
-        # complete checking registers
-        self.quit_testpmd()
-        return res
-
-    def check_GLGEN_GPIO_CTL_value(self, hex_value, target_value):
-        self.verify(
-            hex_value[-3] == target_value,
-            "check register failed, target value is {} not match expected value {}".format(
-                hex_value[-3], target_value
-            ),
-        )
-        bit_5th = bin(int(hex_value, 16))[-5]
-        self.verify(
-            bit_5th == "1",
-            "check register failed, the 5th bit is {} not match expected value {}".format(
-                bit_5th, 1
-            ),
-        )
-        self.logger.info("check register value {} pass".format(hex_value))
-
-    def test_check_register_with_pin_id_0(self):
-        addrs = ["0x00088998", "0x000889B8", "0x00088928", "0x00088930", "0x000880C8"]
-        res = self.check_four_registers(pin_id=0, addrs=addrs)
-        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[0] 0x000880C8 is 8. And the 5th binary digit is 1.
-        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group("hex"), target_value="8")
-
-    def test_check_register_with_pin_id_1(self):
-        addrs = ["0x000889A0", "0x000889C0", "0x00088938", "0x00088940", "0x000880CC"]
-        res = self.check_four_registers(pin_id=1, addrs=addrs)
-        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[1] 0x000880CC is 9. And the 5th binary digit is 1.
-        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group("hex"), target_value="9")
-
-    def test_check_register_with_pin_id_2(self):
-        addrs = ["0x000889A8", "0x000889C8", "0x00088948", "0x00088950", "0x000880D0"]
-        res = self.check_four_registers(pin_id=2, addrs=addrs)
-        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[2] 0x000880D0 is A. And the 5th binary digit is 1.
-        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group("hex"), target_value="A")
-
-    def test_check_register_with_pin_id_3(self):
-        addrs = ["0x000889B0", "0x000889D0", "0x00088958", "0x00088960", "0x000880D4"]
-        res = self.check_four_registers(pin_id=3, addrs=addrs)
-        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[3] 0x000880D4 is B. And the 5th binary digit is 1.
-        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group("hex"), target_value="B")
-
-    def quit_testpmd(self):
-        self.pmd_output.quit()
-
-    def tear_down(self):
-        self.dut.kill_all()
-
-    def tear_down_all(self):
-        self.dut.kill_all()
-- 
2.25.1


^ permalink raw reply	[flat|nested] 5+ messages in thread
* [dts][PATCH V1] tests/ice_1pps_signal: remove suite and test plan due to dpdk22.11 changes
@ 2022-12-29  6:39 Yu Jiang
  2023-01-03  5:46 ` Fu, Qi
  2023-01-04  1:24 ` lijuan.tu
  0 siblings, 2 replies; 5+ messages in thread
From: Yu Jiang @ 2022-12-29  6:39 UTC (permalink / raw)
  To: qi.fu, dts; +Cc: Yu Jiang

According to dpdk22.11 commit 1bcb7ba9 ("app/testpmd: drop PCI register commands"),
reading and setting port registers related cmds have been removed from dpdk. 

Signed-off-by: Yu Jiang <yux.jiang@intel.com>
---
 test_plans/ice_1pps_signal_test_plan.rst | 131 -----------------------
 test_plans/index.rst                     |   1 -
 tests/TestSuite_ice_1pps_signal.py       | 128 ----------------------
 3 files changed, 260 deletions(-)
 delete mode 100644 test_plans/ice_1pps_signal_test_plan.rst
 delete mode 100644 tests/TestSuite_ice_1pps_signal.py

diff --git a/test_plans/ice_1pps_signal_test_plan.rst b/test_plans/ice_1pps_signal_test_plan.rst
deleted file mode 100644
index 1c7c4d8a..00000000
--- a/test_plans/ice_1pps_signal_test_plan.rst
+++ /dev/null
@@ -1,131 +0,0 @@
-.. SPDX-License-Identifier: BSD-3-Clause
-   Copyright(c) 2021 Intel Corporation
-
-=========================
-ICE 1PPS Signal Test Plan
-=========================
-
-Description
-===========
-The Intel® Ethernet 800 Series supports a total of four single-ended GPIO signals(SPD[20:23])plus
-one different GPIO signal (CLK_OUT_P/N), which is configured by default 1PPS(out). The SPD[20:23]
-is mapping to pin_id[0:3]. This test plan is designed to check the value of related registers,
-which make up the 1PPS signal. The registers address depends on some hardware config.
-The test cases only give the example of E810-XXVDA4 and E810-CQ.
-
-
-Prerequisites
-=============
-
-Topology
---------
-DUT port 0 <----> Tester port 0
-
-Hardware
---------
-Supported NICs: Intel® Ethernet 800 Series E810-XXVDA4/E810-CQ
-
-Software
---------
-dpdk: http://dpdk.org/git/dpdk
-scapy: http://www.secdev.org/projects/scapy/
-
-General set up
---------------
-1. Compile DPDK::
-
-    # CC=gcc meson --werror -Denable_kmods=True -Dlibdir=lib --default-library=static <dpdk build dir>
-    # ninja -C <dpdk build dir> -j 110
-
-2. Get the pci device id and interface of DUT and tester.
-   For example, 0000:18:00.0 and 0000:18:00.1 is pci device id,
-   ens785f0 and ens785f1 is interface::
-
-    <dpdk dir># ./usertools/dpdk-devbind.py -s
-
-    0000:18:00.0 'Device 159b' if=ens785f0 drv=ice unused=vfio-pci
-    0000:18:00.1 'Device 159b' if=ens785f1 drv=ice unused=vfio-pci
-
-3. Bind the DUT port to dpdk::
-
-    <dpdk dir># ./usertools/dpdk-devbind.py -b vfio-pci <DUT port pci device id>
-
-
-Test case
-=========
-
-Test case 1: check registers when pin id is 0
----------------------------------------------
-
-this case is designed to check the register value is right when pin id is 0.
-
-test steps
-~~~~~~~~~~
-1. start testpmd with different pin_id and dump registers::
-
-    <dpdk build dir>/app/dpdk-testpmd <EAL options> -a <DUT port pci device id>,pps_out='[pin:0]' -- -i --rxq=4 --txq=4
-    testpmd> read reg 0 0x00088998
-    testpmd> read reg 0 0x000889B8
-    testpmd> read reg 0 0x00088928
-    testpmd> read reg 0 0x00088930
-    testpmd> read reg 0 0x000880C8
-
-2. check the GLTSYN_AUX_OUT_0[0] 0x00088998 is 0x00000007 (7), GLTSYN_CLKO_0[0] 0x000889B8 is 0x1DCD6500 (500000000), the 0x00088928 and 0x00088930 is non-zero,
-   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[0] 0x000880C8 is 8. And the 5th binary digit is 1.
-
-Test case 2: check registers when pin id is 1
----------------------------------------------
-
-this case is designed to check the register value is right when pin id is 1.
-
-test steps
-~~~~~~~~~~
-1. start testpmd with different pin_id and dump registers::
-
-    ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:1]' -- -i --rxq=4 --txq=4
-    testpmd> read reg 0 0x000889A0
-    testpmd> read reg 0 0x000889C0
-    testpmd> read reg 0 0x00088938
-    testpmd> read reg 0 0x00088940
-    testpmd> read reg 0 0x000880CC
-
-2. check the GLTSYN_AUX_OUT_1[0] 0x000889A0 is 0x00000007 (7), GLTSYN_CLKO_1[0] 0x000889C0 is 0x1DCD6500 (500000000), the 0x00088938 and 0x00088940 is non-zero,
-   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[1] 0x000880CC is 9. And the 5th binary digit is 1.
-
-Test case 3: check registers when pin id is 2
----------------------------------------------
-
-this case is designed to check the register value is right when pin id is 2.
-
-test steps
-~~~~~~~~~~
-1. start testpmd with different pin_id and dump registers::
-
-    ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:2]' -- -i --rxq=4 --txq=4
-    testpmd> read reg 0 0x000889A8
-    testpmd> read reg 0 0x000889C8
-    testpmd> read reg 0 0x00088948
-    testpmd> read reg 0 0x00088950
-    testpmd> read reg 0 0x000880D0
-
-2. check the GLTSYN_AUX_OUT_2[0] 0x000889A8 is 0x00000007 (7), GLTSYN_CLKO_2[0] 0x000889C8 is 0x1DCD6500 (500000000), the 0x00088948 and 0x00088950 is non-zero,
-   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[2] 0x000880D0 is A. And the 5th binary digit is 1.
-
-Test case 4: check registers when pin id is 3
----------------------------------------------
-
-this case is designed to check the register value is right when pin id is 3.
-
-test steps
-~~~~~~~~~~
-1. start testpmd with different pin_id and dump registers::
-
-    ./x86_64-native-linuxapp-gcc/app/dpdk-testpmd -c 0xf -n 4 -a 0000:18:00.0,pps_out='[pin:3]' -- -i --rxq=4 --txq=4
-    testpmd> read reg 0 0x000889B0
-    testpmd> read reg 0 0x000889D0
-    testpmd> read reg 0 0x00088958
-    testpmd> read reg 0 0x00088960
-    testpmd> read reg 0 0x000880D4
-
-2. check the GLTSYN_AUX_OUT_3[0] 0x000889B0 is 0x00000007 (7), GLTSYN_CLKO_3[0] 0x000889D0 is 0x1DCD6500 (500000000), the 0x00088958 and 0x00088960 is non-zero,
-   The 3rd Hexadecimal digit of GLGEN_GPIO_CTL[3] 0x000880D4 is B. And the 5th binary digit is 1.
\ No newline at end of file
diff --git a/test_plans/index.rst b/test_plans/index.rst
index 9ca954e2..d2552f22 100644
--- a/test_plans/index.rst
+++ b/test_plans/index.rst
@@ -54,7 +54,6 @@ The following are the test plans for the DPDK DTS automated test system.
     ice_switch_filter_test_plan
     ice_switch_filter_pppoe_test_plan
     ice_vf_support_multicast_address_test_plan
-    ice_1pps_signal_test_plan
     ice_rss_protocol_agnostic_flow_test_plan
     ice_fdir_protocol_agnostic_flow_test_plan
     cloud_filter_with_l4_port_test_plan
diff --git a/tests/TestSuite_ice_1pps_signal.py b/tests/TestSuite_ice_1pps_signal.py
deleted file mode 100644
index ef94d466..00000000
--- a/tests/TestSuite_ice_1pps_signal.py
+++ /dev/null
@@ -1,128 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(c) 2010-2022 Intel Corporation
-#
-
-import re
-
-from framework.pmd_output import PmdOutput
-from framework.test_case import TestCase, check_supported_nic
-
-
-class TestICE1PPS(TestCase):
-    supported_nic = ["ICE_100G-E810C_QSFP", "ICE_25G-E810C_SFP", "ICE_25G-E810_XXV_SFP"]
-
-    @check_supported_nic(supported_nic)
-    def set_up_all(self):
-        """
-        Run at the start of each test suite.
-        prerequisites.
-        """
-        # Based on h/w type, chose how many ports to use
-        dut_ports = self.dut.get_ports(self.nic)
-        self.verify(len(dut_ports) >= 1, "Insufficient ports for testing")
-        # Verify that enough threads are available
-        self.cores = self.dut.get_core_list("1S/2C/1T")
-        self.verify(self.cores, "Insufficient cores for speed testing")
-        self.pci = self.dut.ports_info[dut_ports[0]]["pci"]
-        self.pmd_output = PmdOutput(self.dut)
-        self.GLTSYN_AUX = re.compile(r"0x00000007\s+\(7\)")
-        self.GLTSYN_CLKO = re.compile(r"0x1DCD6500\s+\(500000000\)")
-        self.pattern = re.compile(
-            "register\s+at\s+offset\s+.*:\s+(?P<hex>0x\w+)\s+\(\d+\)"
-        )
-
-    def set_up(self):
-        """
-        Run before each test case.
-        """
-        pass
-
-    def read_register(self, addr, port_id=0):
-        cmd = "read reg {} {}".format(port_id, addr)
-        return self.pmd_output.execute_cmd(cmd)
-
-    def launch_testpmd(self, pin_id, rxq=4, txq=4):
-        self.out = self.pmd_output.start_testpmd(
-            cores="1S/2C/1T",
-            param="--rxq={} --txq={} ".format(rxq, txq),
-            eal_param="-a {},pps_out='[pin:{}]'".format(self.pci, pin_id),
-        )
-        # Check the GLTSYN_AUX_OUT, GLTSYN_CLKO and other two registers
-
-    def check_four_registers(self, pin_id, addrs, port_id=0):
-        self.launch_testpmd(pin_id)
-        for i in range(len(addrs)):
-            out = self.read_register(addrs[i], port_id=port_id)
-            if i == 0:
-                pattern = self.GLTSYN_AUX
-            elif i == 1:
-                pattern = self.GLTSYN_CLKO
-            else:
-                pattern = self.pattern
-            res = pattern.search(out)
-            self.verify(
-                res, "pattern:{} not found in output info: {}".format(pattern, out)
-            )
-            if i > 1:
-                actual_value = int(res.group("hex"), 16)
-                self.verify(
-                    actual_value != 0,
-                    "check pin id:{0} register address:{1} failed, expected value is non-zero, actual value is:{2}".format(
-                        pin_id, addrs[i], actual_value
-                    ),
-                )
-            self.logger.info(
-                "check pin id: {0} register address: {1} pass".format(pin_id, addrs[i])
-            )
-        # complete checking registers
-        self.quit_testpmd()
-        return res
-
-    def check_GLGEN_GPIO_CTL_value(self, hex_value, target_value):
-        self.verify(
-            hex_value[-3] == target_value,
-            "check register failed, target value is {} not match expected value {}".format(
-                hex_value[-3], target_value
-            ),
-        )
-        bit_5th = bin(int(hex_value, 16))[-5]
-        self.verify(
-            bit_5th == "1",
-            "check register failed, the 5th bit is {} not match expected value {}".format(
-                bit_5th, 1
-            ),
-        )
-        self.logger.info("check register value {} pass".format(hex_value))
-
-    def test_check_register_with_pin_id_0(self):
-        addrs = ["0x00088998", "0x000889B8", "0x00088928", "0x00088930", "0x000880C8"]
-        res = self.check_four_registers(pin_id=0, addrs=addrs)
-        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[0] 0x000880C8 is 8. And the 5th binary digit is 1.
-        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group("hex"), target_value="8")
-
-    def test_check_register_with_pin_id_1(self):
-        addrs = ["0x000889A0", "0x000889C0", "0x00088938", "0x00088940", "0x000880CC"]
-        res = self.check_four_registers(pin_id=1, addrs=addrs)
-        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[1] 0x000880CC is 9. And the 5th binary digit is 1.
-        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group("hex"), target_value="9")
-
-    def test_check_register_with_pin_id_2(self):
-        addrs = ["0x000889A8", "0x000889C8", "0x00088948", "0x00088950", "0x000880D0"]
-        res = self.check_four_registers(pin_id=2, addrs=addrs)
-        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[2] 0x000880D0 is A. And the 5th binary digit is 1.
-        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group("hex"), target_value="A")
-
-    def test_check_register_with_pin_id_3(self):
-        addrs = ["0x000889B0", "0x000889D0", "0x00088958", "0x00088960", "0x000880D4"]
-        res = self.check_four_registers(pin_id=3, addrs=addrs)
-        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[3] 0x000880D4 is B. And the 5th binary digit is 1.
-        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group("hex"), target_value="B")
-
-    def quit_testpmd(self):
-        self.pmd_output.quit()
-
-    def tear_down(self):
-        self.dut.kill_all()
-
-    def tear_down_all(self):
-        self.dut.kill_all()
-- 
2.25.1


^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-01-04  1:24 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-29  6:35 [dts][PATCH V1] tests/ice_1pps_signal: remove suite and test plan due to dpdk22.11 changes Yu Jiang
2023-01-03  5:45 ` Fu, Qi
2022-12-29  6:39 Yu Jiang
2023-01-03  5:46 ` Fu, Qi
2023-01-04  1:24 ` lijuan.tu

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