* [PATCH V1 4/4] conf/loopback_vhost_async_perf_dsa: add new testsuite config file
@ 2023-02-06 3:39 Wei Ling
0 siblings, 0 replies; only message in thread
From: Wei Ling @ 2023-02-06 3:39 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
Add conf/loopback_vhost_async_perf_dsa.cfg.
Signed-off-by: Wei Ling <weix.ling@intel.com>
---
conf/loopback_vhost_async_perf_dsa.cfg | 405 +++++++++++++++++++++++++
1 file changed, 405 insertions(+)
create mode 100644 conf/loopback_vhost_async_perf_dsa.cfg
diff --git a/conf/loopback_vhost_async_perf_dsa.cfg b/conf/loopback_vhost_async_perf_dsa.cfg
new file mode 100644
index 00000000..af7c7fef
--- /dev/null
+++ b/conf/loopback_vhost_async_perf_dsa.cfg
@@ -0,0 +1,405 @@
+[suite]
+update_expected = True
+test_parameters = {64: [1024], 128: [1024], 256: [1024], 512: [1024], 1024: [1024], 1518: [1024]}
+test_duration = 60
+accepted_tolerance = 1
+expected_throughput = {
+ 'test_loopback_split_ring_inorder_mergedable_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_split_ring_inorder_non_mergedable_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_split_ring_mergedable_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_split_ring_non_mergedable_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_split_ring_vector_rx_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_inorder_mergedable_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_inorder_non_mergedable_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_mergedable_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_non_mergedable_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_vector_rx_idxd': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_split_ring_inorder_mergedable_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_split_ring_inorder_non_mergedable_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_split_ring_mergedable_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_split_ring_non_mergedable_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_split_ring_vector_rx_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_inorder_mergedable_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_inorder_non_mergedable_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_mergedable_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_non_mergedable_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }
+ },
+ 'test_loopback_packed_ring_vector_rx_vfio_pci': {
+ 64: {
+ 1024: 0.00
+ },
+ 128: {
+ 1024: 0.00
+ },
+ 256: {
+ 1024: 0.00
+ },
+ 512: {
+ 1024: 0.00
+ },
+ 1024: {
+ 1024: 0.00
+ },
+ 1518: {
+ 1024: 0.00
+ }}}
--
2.25.1
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