From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70918A3160 for ; Wed, 9 Oct 2019 09:56:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4FD8E1C11A; Wed, 9 Oct 2019 09:56:48 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 016D71C02E for ; Wed, 9 Oct 2019 09:56:46 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Oct 2019 00:56:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,273,1566889200"; d="scan'208";a="196848772" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga003.jf.intel.com with ESMTP; 09 Oct 2019 00:56:45 -0700 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 9 Oct 2019 00:56:45 -0700 Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 9 Oct 2019 00:56:44 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Wed, 9 Oct 2019 00:56:44 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.176]) by SHSMSX151.ccr.corp.intel.com ([10.239.6.50]) with mapi id 14.03.0439.000; Wed, 9 Oct 2019 15:56:43 +0800 From: "Yao, Lei A" To: "Ma, LihongX" , "dts@dpdk.org" Thread-Topic: [dts][PATCH V1] test_plan: add test plan of power pbf Thread-Index: AQHVfXxIUNu0dI5waUue4BNmpjjovKdR8xZA Date: Wed, 9 Oct 2019 07:56:43 +0000 Message-ID: <2DBBFF226F7CF64BAFCA79B681719D95497AE3D4@shsmsx102.ccr.corp.intel.com> References: <1570473375-3772-1-git-send-email-lihongx.ma@intel.com> In-Reply-To: <1570473375-3772-1-git-send-email-lihongx.ma@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMzU0N2VkZGMtMDQ5Yi00Y2YxLWE3YjktMDUxNGE4YTBmMzkzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiRHMwQXZTUVp2Q3QrTGZVbDA3VkM4SVBFcUVycnBpejBkU01wcXBMakkwaDZBVTJEVVBMS3daejN2VGNtTlEzMSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dts] [PATCH V1] test_plan: add test plan of power pbf X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dts-bounces@dpdk.org Sender: "dts" > -----Original Message----- > From: Ma, LihongX > Sent: Tuesday, October 8, 2019 2:36 AM > To: dts@dpdk.org > Cc: Yao, Lei A ; Ma, LihongX > Subject: [dts][PATCH V1] test_plan: add test plan of power pbf >=20 > Signed-off-by: lihong Acked-by: lei yao > --- > test_plans/power_pbf_test_plan.rst | 191 > +++++++++++++++++++++++++++++++++++++ > 1 file changed, 191 insertions(+) > create mode 100644 test_plans/power_pbf_test_plan.rst >=20 > diff --git a/test_plans/power_pbf_test_plan.rst > b/test_plans/power_pbf_test_plan.rst > new file mode 100644 > index 0000000..2ec3e56 > --- /dev/null > +++ b/test_plans/power_pbf_test_plan.rst > @@ -0,0 +1,191 @@ > +.. Copyright (c) <2019>, Intel Corporation > + All rights reserved. > + > + Redistribution and use in source and binary forms, with or without > + modification, are permitted provided that the following conditions > + are met: > + > + - Redistributions of source code must retain the above copyright > + notice, this list of conditions and the following disclaimer. > + > + - Redistributions in binary form must reproduce the above copyright > + notice, this list of conditions and the following disclaimer in > + the documentation and/or other materials provided with the > + distribution. > + > + - Neither the name of Intel Corporation nor the names of its > + contributors may be used to endorse or promote products derived > + from this software without specific prior written permission. > + > + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND > CONTRIBUTORS > + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT > NOT > + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND > FITNESS > + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE > + COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, > INDIRECT, > + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES > + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE > GOODS OR > + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) > + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > CONTRACT, > + STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF > ADVISED > + OF THE POSSIBILITY OF SUCH DAMAGE. > + > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +Power PBF Tests > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +PBF(Priority Base Frequency) is new power feature on some Intel CPU > +SKU. This feature can support some core in core list have garenteed > +higher base frequency DPDK start support this feature from 19.05 > + > +Preparation work > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +Check the SKU of Processor: 6230N, 6252N and 5218N can support this > +feature 1. Turn on Speedstep option in BIOS 2. Set C-State to C0/C1 3. > +Turn on Turbo in BIOS 4. Turn on PBF in BIOS 5. Set HW Pstate to > +"Native Mode without Legacy Support" > +6. Turn on RAPL Prioritization > +7. Modprobe msr module > +8. DON'T set intel_pstate to disable in grub 9. Turn on the debug log > +for DPDK power lib, CONFIG_RTE_LIBRTE_POWER_DEBUG=3Dy > + > +Test Case1 : Check High Priority Core Can Be Recognized By Power Lib > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +Step 1. Create powermonitor fold for:: > + > + Create power monitor channel folder, /tmp/powermonitor, give > + permission for read and write > + > +Step 2. Compile DPDK with Power Lib debug info on, then Luanch VM > power manager sample:: > + > + ./examples/vm_power_manager/build/vm_power_mgr -l 1-4 -n 4 > + --file-prefix=3Dpower --no-pci > + > + Check two different base_max frequency will be shown in log, for > example on Intel 6230N Processor: > + The log will be like as following > + POWER: power_get_available_freqs: sys min 800000, sys max 3900000, > base_max 2300000 > + POWER: power_get_available_freqs: sys min 800000, sys max 3900000, > + base_max 2700000 > + > + For each core, get following 3 frequency item, cross check frequency= in > the VM_power out put log: > + sys_min=3Dsys/devices/system/cpu/cpu{}/cpufreq/cpuinfo_min_freq > + sys_max=3Dsys/devices/system/cpu/cpu{}/cpufreq/cpuinfo_max_freq > + base_max=3Dsys/devices/system/cpu/cpu{}/cpufreq/base_frequency > + > + Take Intel 6230N Processor as example: > + sys_min=3D800000 > + sys_max=3D3900000 > + base_max=3D2700000(high priority Core) base_max=3D2300000 (Normal Co= re) > + > + The high priority core has max frequency at 27000000 > + Normal core has max frequency at 2300000 > + > +Test Case2 : CPU MIN and MAX Freq Test for the High Priority Core > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D > +Step 1. Create powermonitor fold for:: > + > + Create monitor channel folder, /tmp/powermonitor, give permission > + for read and write > + > +Step 2. Compile DPDK with Power Lib debug info on, then aunch VM power > manager sample:: > + > + ./examples/vm_power_manager/build/vm_power_mgr -l 1-4 -n 4 > + --file-prefix=3Dpower --no-pci > + > +Step 3. Prepare different command in JSON format:: > + > + From Test Case1, can get the high priority core list. We pick one co= re from > this list > + Command JSON file template: > + {"instruction": { > + "name": "policy1", > + "command": "power", > + "unit": "SCALE_MIN", > + }} > + > +Step 4: Send different command to power sample, then check the > frequency:: > + > + Command Steps: ENABLE_TURBO-> SCALE_MAX-> SCALE_DOWN-> > SCALE_MIN > + Send action JSON file to vm_power_mgr's fifo channel, each core will > have it's own channel: > + cat command.json >/tmp/powermonitor/fifo{core_number} > + > + Check the CPU frequency is changed accordingly in previous list by > following method: > + min=3Dsys/devices/system/cpu/cpu{}/cpufreq/scaling_min_freq > + max=3Dsys/devices/system/cpu/cpu{}/cpufreq/scaling_max_freq > + Step SCALE_MAX: min=3Dmax=3Dsys_max > + Step SCALE_DOWN: min=3Dmax=3Dbase_max > + Step SCALE_MIN: min=3Dmax=3Dsys_min > + > + > + More info about the command: > + :"SCALE_MAX": Scale frequency of this core to maximum > + :"SCALE_MIN": Scale frequency of this core to minimum > + :"SCALE_UP": Scale up frequency of this core > + :"SCALE_DOWN": Scale down frequency of this core > + :"ENABLE_TURBO": Enable Turbo Boost for this core > + :"DISABLE_TURBO": Disable Turbo Boost for this core > + > +Test Case3 : Check "DISABLE_TURBO" Action When Core is In Turbo Status > +for High Priority Core > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +Step 1. Create powermonitor fold for:: > + > + Create monitor channel folder, /tmp/powermonitor, give permission > + 777 > + > +Step 2. Compile DPDK with Power Lib debug info on, then launch VM power > manager sample:: > + > + ./examples/vm_power_manager/build/vm_power_mgr -l 1-4 -n 4 > + --file-prefix=3Dpower --no-pci > + > +Step 3. Prepare Several command in JSON format then send it to the fifo > channel for the high priority core:: > + > + {"instruction": { > + "name": "policy2", > + "command": "power", > + "unit": "SCALE_MIN", > + }} > + cat command.json >/tmp/powermonitor/fifo{core_number} > + > + Command Steps: ENABLE_TURBO -> SCALE_MAX ->DISABLE_TURBO > + > +Step 4. Check the CPU frequency will be set to No turbo max frequency > when turbo is off:: > + > + min=3Dsys/devices/system/cpu/cpu{}/cpufreq/scaling_min_freq > + max=3Dsys/devices/system/cpu/cpu{}/cpufreq/scaling_max_freq > + Check point of Step SCALE_MAX: min=3Dmax=3Dsys_max > + Check point of Step DISABLE_TURBO: min=3Dmax=3Dbase_max > + > + > +Test Case4: Check Distributor Sample Use High Priority Core as > +Distribute Core > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Step 1. Get the Priority c= ore list on DUT in test case > +1:: > + > + For example: > + 6,7,13,14,15,16,21,26,27,29,36,38 > + On one Intel 6230N Processor > + Note: the high base frequency core location of each processor is dif= ferent. > + > +Step 2. Launch distributor with 1 priority core, check the high priority= core > will be picked as the distributor core:: > + > + Two worker: > + ./distributor_app -l 1-6 -n 4 -- -p 0x1 > + > + Check the high priority core is assigned as distributor core in log,= for > example: > + "Core 6 acting as distributor core." > + > +Test Case5: Check Distributor Sample Will use High priority core for > +distribute core and rx/tx core > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D Step 1. Get the Priority core list on > DUT > +in test case 1:: > + > + Using pbf.py to check, or check from kernel > + For example: > + 6,7,13,14,15,16,21,26,27,29,36,38 > + On one intel 6230N Processor > + Note: the high base frequency core location of each processor are > different. > + > +Step 2. Launch distributor with 3 priority core, check the high > +priority core will be picked as the distributor core, rx and tx core:: > + > + For example, the high priority core is" 6,7 13" > + ./distributor_app -l 1-6,7,13 -n 4 -- -p 0x1 > + > +Step 3. Check the high priority core is assigned as distributor core in = log, for > example:: > + > + Distributor on priority core 6 > + > +Step 4. Check the high priority core are assigned as tx/rx core in log, = for > example:: > + > + Core 13 doing packet TX. > + Core 7 doing packet RX. > -- > 2.7.4