From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 19E531B135 for ; Fri, 19 Oct 2018 04:55:05 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Oct 2018 19:55:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,398,1534834800"; d="scan'208";a="96533060" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga002.fm.intel.com with ESMTP; 18 Oct 2018 19:55:04 -0700 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 18 Oct 2018 19:55:04 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 18 Oct 2018 19:55:04 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.60]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.183]) with mapi id 14.03.0319.002; Fri, 19 Oct 2018 10:55:00 +0800 From: "Tu, Lijuan" To: "Wang, FeiX Y" , "dts@dpdk.org" Thread-Topic: [dts] [PATCH V3 2/3] add test suite for performance thread Thread-Index: AQHUZsA0ptUwevzG90G8bjzqTTokEKUl2dWw Date: Fri, 19 Oct 2018 02:54:59 +0000 Message-ID: <8CE3E05A3F976642AAB0F4675D0AD20E0B97BCAD@SHSMSX101.ccr.corp.intel.com> References: <20181018153851.36535-1-feix.y.wang@intel.com> In-Reply-To: <20181018153851.36535-1-feix.y.wang@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjU1MWUxMDEtNGMzZS00YmE4LTkyYzgtYzEyODQ3YjFhMmU3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiY0pNbVZaSHBcL3ByK3N4akZhQVJSeGVUQXRMeGdXYUkycVdvdmZyYkRFWkRYSkRXOUIyeVhGSDBRSFlydG43elUifQ== x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dts] [PATCH V3 2/3] add test suite for performance thread X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Oct 2018 02:55:06 -0000 test_perf_one_lcore_per_pcore / test_perf_n_lcore_per_pcore I think the 2 cases is only different between 1 and N, but I get your argum= ent are different, one is using coremask, and the other using lcore. More comments inline. > -----Original Message----- > From: Wang, FeiX Y > Sent: Thursday, October 18, 2018 11:39 PM > To: dts@dpdk.org > Cc: Tu, Lijuan ; Wang, FeiX Y > Subject: [dts] [PATCH V3 2/3] add test suite for performance thread >=20 > From: wang fei >=20 > Signed-off-by: wang fei > --- > tests/TestSuite_performance_thread.py | 249 > ++++++++++++++++++++++++++ > 1 file changed, 249 insertions(+) > create mode 100644 tests/TestSuite_performance_thread.py >=20 > diff --git a/tests/TestSuite_performance_thread.py > b/tests/TestSuite_performance_thread.py > new file mode 100644 > index 0000000..b00e8a4 > --- /dev/null > +++ b/tests/TestSuite_performance_thread.py > @@ -0,0 +1,249 @@ > +# BSD LICENSE > +# > +# Copyright(c) 2010-2014 Intel Corporation. All rights reserved. > +# All rights reserved. > +# > +# Redistribution and use in source and binary forms, with or without # > +modification, are permitted provided that the following conditions # > +are met: > +# > +# * Redistributions of source code must retain the above copyright > +# notice, this list of conditions and the following disclaimer. > +# * Redistributions in binary form must reproduce the above copyright > +# notice, this list of conditions and the following disclaimer in > +# the documentation and/or other materials provided with the > +# distribution. > +# * Neither the name of Intel Corporation nor the names of its > +# contributors may be used to endorse or promote products derived > +# from this software without specific prior written permission. > +# > +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND > CONTRIBUTORS # > +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT > NOT # > +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND > FITNESS FOR # > +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE > COPYRIGHT # > +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, > INCIDENTAL, # > +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > NOT # > +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS > OF USE, # > +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND > ON ANY # > +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR > TORT # > +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF > THE USE # > +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH > DAMAGE. > + > +""" > +DPDK Test suite. > +Performance-Thread test script. > +""" > + > +import utils > + > +from test_case import TestCase > +from settings import HEADER_SIZE > +from etgen import IxiaPacketGenerator > + > +class TestPerformanceThread(TestCase, IxiaPacketGenerator): > + > + def set_up_all(self): > + self.ports =3D self.dut.get_ports() > + self.verify(len(self.ports) >=3D 2, "Insufficent Ports") > + self.socket =3D self.dut.get_numa_id(self.ports[0]) > + self.port0_mac =3D self.dut.get_mac_address(self.ports[0]) > + self.port1_mac =3D self.dut.get_mac_address(self.ports[1]) > + > + > + self.tester.extend_external_packet_generator(TestPerformanceThread, > + self) > + > + self.frame_sizes =3D [64, 128, 256, 512, 1024, 2000] [Lijuan] I thinks frame size can be moved to configuration file. > + self.headers_size =3D HEADER_SIZE['eth'] + HEADER_SIZE['ip'] + > HEADER_SIZE['tcp'] > + self.nb_cores =3D self.get_suite_cfg()["cores"] > + self.path =3D > "examples/performance-thread/l3fwd-thread/build/l3fwd-thread" > + > + #results table header > + self.header =3D ["Cores", "Fsize", "Unidirectional MPPS", "Line > + Rate(%)", "Bidirectional MPPS", "Line Rate(%)"] > + > + # compile performance_thread app > + out =3D > self.dut.build_dpdk_apps("./examples/performance-thread/l3fwd-thread") > + self.verify("Error" not in out, "compilation error 1") > + self.verify("No such file" not in out, "compilation error 2") > + > + def set_up(self): > + pass > + > + def test_perf_one_lcore_per_pcore(self): > + nb_cores =3D self.nb_cores > + params =3D "-n 2 -- -P -p 3 --enable-jumbo --max-pkt-len=3D2500 [Lijuan] Could you calculate the max-pkt-len, max(frame_sizes) + 200 is mor= e reasonable. "-n 2", the memory channel is configured in crb.cfg, so please utilize self= .dut.get_memory_channels() to get the memory channels > --no-lthread" > + test_data =3D {} > + for cores in nb_cores: > + _, core_mask =3D self.create_cores(cores) > + _,rx, tx =3D self.config_rx_tx(cores) > + app_cmdline =3D "{} -c {} {} --rx=3D'{}' --tx=3D'{}'".format= (self.path, > core_mask, params, rx, tx) > + self.dut.send_expect(app_cmdline, "", 15) > + test_data[cores] =3D self.start_traffic() > + self.dut.send_expect("^C", "# ", 15) > + self.print_result(test_data) > + > + def test_perf_n_lthreads_per_pcore(self): > + nb_cores =3D self.nb_cores > + params =3D "-n 2 -- -P -p 3 --enable-jumbo --max-pkt-len=3D2500" > + test_data =3D {} > + for cores in nb_cores: > + _, core_mask =3D self.create_cores(cores) > + _,rx, tx =3D self.config_rx_tx(cores) > + app_cmdline =3D "{} -c {} {} --rx=3D'{}' --tx=3D'{}'".format= (self.path, > core_mask, params, rx, tx) > + self.dut.send_expect(app_cmdline, "", 15) > + test_data[cores] =3D self.start_traffic() > + self.dut.send_expect("^C", "# ", 15) > + self.print_result(test_data) > + > + def test_perf_n_lcore_per_pcore(self): > + nb_cores =3D self.nb_cores > + params =3D "-- -P -p 3 --enable-jumbo --max-pkt-len 2500 > --no-lthread" > + test_data =3D {} > + for cores in nb_cores: > + _, core_mask =3D self.create_cores(cores) > + rxtx_config, rx, tx =3D self.config_rx_tx(cores) > + #app_cmdline =3D "{} -c {} -n 2 --lcores=3D'{}' {} --rx=3D'{= }' > --tx=3D'{}'".format(self.path, core_mask, rxtx_config, params, rx, tx) > + app_cmdline =3D "{} -n 2 --lcores=3D'{}' {} --rx=3D'{}' > --tx=3D'{}'".format(self.path, rxtx_config, params, rx, tx) [Lijuan] please remove your draft information > + self.dut.send_expect(app_cmdline, "", 15) > + test_data[cores] =3D self.start_traffic() > + self.dut.send_expect("^C", "# ", 15) > + self.print_result(test_data) > + > + def create_cores(self, nb_cores): > + if nb_cores =3D=3D 2: > + core_config =3D "1S/2C/1T" > + elif nb_cores =3D=3D 4: > + core_config =3D "1S/4C/1T" > + elif nb_cores =3D=3D 8: > + core_config =3D "1S/8C/1T" > + elif nb_cores =3D=3D 16: > + core_config =3D "1S/16C/1T" > + core_list =3D self.dut.get_core_list(core_config, self.socket) > + core_mask =3D utils.create_mask(core_list) > + return core_list, core_mask > + > + def config_rx_tx(self, cores): > + socket =3D self.socket > + ports =3D range(len(self.ports)) > + tx_config =3D "" > + rx_config =3D "" > + core_mask =3D "" > + lcore_config =3D "" > + assert cores in self.nb_cores > + > + #config --tx and --tx params for performace thread app > + if cores =3D=3D 2: > + core_list, core_mask =3D self.create_cores(cores) > + lcore_config =3D "(%s-%s)@%s" % (core_list[0],core_list[-1], > core_list[0]) > + rx =3D "({},{},{},{})".format(ports[0], 0, core_list[0], 0) = + "," + \ > + "({},{},{},{})".format(ports[1], 0, core_list[0], 0) > + tx =3D "({},{})".format(core_list[1], 0) > + elif cores =3D=3D 4: > + core_list, core_mask =3D self.create_cores(cores) > + lcore_config =3D "(%s-%s)@%s" % (core_list[0], core_list[-1]= , > core_list[0]) > + rx =3D "({},{},{},{})".format(ports[0], 0, core_list[0], 0) = + "," + \ > + "({},{},{},{})".format(ports[1], 0, core_list[1], 1) > + tx =3D "({},{})".format(core_list[2], 0) + "," + \ > + "({},{})".format(core_list[3], 1) > + elif cores =3D=3D 8: > + core_list, core_mask =3D self.create_cores(cores) > + lcore_config =3D "(%s-%s)@%s" % (core_list[0], core_list[-1]= , > core_list[0]) > + rx =3D "({},{},{},{})".format(ports[0], 0, core_list[0], 0) = + "," + \ > + "({},{},{},{})".format(ports[0], 1, core_list[1], 1) + = "," + > \ > + "({},{},{},{})".format(ports[1], 0, core_list[2], 2) + = "," + > \ > + "({},{},{},{})".format(ports[1], 1, core_list[3], 3) > + tx =3D "({},{})".format(core_list[4], 0) + "," + > "({},{})".format(core_list[5], 1) + "," + \ > + "({},{})".format(core_list[6], 2) + "," + > "({},{})".format(core_list[7], 3) > + elif cores =3D=3D 16: > + core_list, core_mask =3D self.create_cores(cores) > + lcore_config =3D "(%s-%s)@%s" % (core_list[0], core_list[-1]= , > core_list[0]) > + rx =3D "({},{},{},{})".format(ports[0], 0, core_list[0], 0) = + "," + \ > + "({},{},{},{})".format(ports[0], 1, core_list[1], 1) + = "," + > \ > + "({},{},{},{})".format(ports[0], 2, core_list[2], 2) + = "," + > \ > + "({},{},{},{})".format(ports[0], 3, core_list[3], 3) + = "," + > \ > + "({},{},{},{})".format(ports[1], 0, core_list[4], 4) + = "," + > \ > + "({},{},{},{})".format(ports[1], 1, core_list[5], 5) + = "," + > \ > + "({},{},{},{})".format(ports[1], 2, core_list[6], 6) + = "," + > \ > + "({},{},{},{})".format(ports[1], 3, core_list[7], 7) > + tx =3D "({},{})".format(core_list[8], 0) + "," + > "({},{})".format(core_list[9], 1) + "," + \ > + "({},{})".format(core_list[10], 2) + "," + > "({},{})".format(core_list[11], 3) + "," + \ > + "({},{})".format(core_list[12], 4) + "," + > "({},{})".format(core_list[13], 5) + "," + \ > + "({},{})".format(core_list[14], 6) + "," + > "({},{})".format(core_list[15], 7) > + return lcore_config, rx, tx > + > + def start_traffic(self): > + frame_sizes =3D self.frame_sizes > + headers_size =3D self.headers_size > + ports =3D self.ports > + dmac0 =3D self.port0_mac > + dmac1 =3D self.port1_mac > + > + tgen_input_unidirection =3D [] > + > tgen_input_unidirection.append((self.tester.get_local_port(ports[0]), > + self.tester.get_local_port(ports[1]), > + "stream0.pcap")) > + > + tgen_input_bidirection =3D [] > + > tgen_input_bidirection.append((self.tester.get_local_port(ports[0]), > + > self.tester.get_local_port(ports[1]), > + "stream0.pcap")) > + > tgen_input_bidirection.append((self.tester.get_local_port(ports[1]), > + > self.tester.get_local_port(ports[0]), > + "stream1.pcap")) > + > + result_data =3D {} > + for frame_size in frame_sizes: > + # create pcap file > + payload_size =3D frame_size - headers_size > + self.tester.scapy_append( > + 'wrpcap("stream0.pcap", > [Ether(src=3D"52:00:00:00:00:00",dst=3D"%s")/IP(src=3D"1.2.3.4",dst=3D"2.= 1.1.1")/TC > P()/("X"*%d)])' % > + (dmac0, payload_size)) > + self.tester.scapy_execute() > + self.logger.info("Starting Uni-Direction Traffic For Frame > Size: %s" % frame_size) > + _, pps =3D > self.tester.traffic_generator_throughput(tgen_input_unidirection, > rate_percent=3D100, delay=3D20) > + mpps =3D pps / 1000000.0 > + self.verify( mpps !=3D 0, "Traffic Blocked") > + wirespeed =3D self.wirespeed(self.nic, frame_size, 1) > + rate =3D (mpps / wirespeed) * 100 > + result_data[frame_size] =3D [mpps, rate] > + > + self.logger.info("Starting Bi-direction Traffic For Frame > Size: %s" % frame_size) > + self.tester.scapy_append( > + 'wrpcap("stream1.pcap", > [Ether(src=3D"52:00:00:00:00:00",dst=3D"%s")/IP(src=3D"1.2.3.4",dst=3D"1.= 1.1.1")/TC > P()/("X"*%d)])' % ( > + dmac1, payload_size)) > + self.tester.scapy_execute() > + _, pps =3D > self.tester.traffic_generator_throughput(tgen_input_bidirection, > rate_percent=3D100, delay=3D20) > + mpps =3D pps / 1000000.0 > + self.verify( mpps !=3D 0, "Traffic Blocked") > + wirespeed =3D self.wirespeed(self.nic, frame_size, 2) > + rate =3D (mpps / wirespeed) * 100 > + result_data[frame_size].extend([mpps, rate]) > + > + return result_data > + > + def print_result(self, data): > + ''' > + print test result table > + ''' > + header =3D self.header > + frame_sizes =3D self.frame_sizes > + nb_cores =3D self.nb_cores > + > + self.result_table_create(header) > + try: > + for nb_core in nb_cores: > + for frame_size in frame_sizes: > + row =3D [nb_core, frame_size] > + row.extend(data[nb_core][frame_size]) > + self.result_table_add(row) > + self.result_table_print() > + except: > + raise > + > + def tear_down(self): > + pass > + > + def tear_down_all(self): > + pass > + > -- > 2.17.1