make pktgen trex port mapping to be compatible with pci address mapping sytle. It is aimed to avoid change ODC current pktgen config files when next branch is merged back to master branch. yufengmx (1): [next]dts/pktgen: add support pci address mapping sytle framework/dut.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.21.0
make pktgen trex port mapping to be compatible with pci address mapping sytle. Signed-off-by: yufengmx <yufengx.mo@intel.com> --- framework/dut.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/framework/dut.py b/framework/dut.py index fc4a2e6..c2ed0f1 100644 --- a/framework/dut.py +++ b/framework/dut.py @@ -986,7 +986,8 @@ class Dut(Crb): if peer is not None: for remotePort in range(len(self.tester.ports_info)): if self.tester.ports_info[remotePort]['type'].lower() == 'trex': - if self.tester.ports_info[remotePort]['intf'].lower() == peer.lower(): + if self.tester.ports_info[remotePort]['intf'].lower() == peer.lower() or \ + self.tester.ports_info[remotePort]['pci'].lower() == peer.lower(): hits[remotePort] = True self.ports_map[dutPort] = remotePort break -- 2.21.0
Tested by Mo, YufengX <yufengx.mo@intel.com>
> -----Original Message-----
> From: Mo, YufengX
> Sent: Monday, September 23, 2019 2:52 PM
> To: dts@dpdk.org; Chen, Zhaoyan <zhaoyan.chen@intel.com>; Tu, Lijuan <lijuan.tu@intel.com>
> Cc: Mo, YufengX <yufengx.mo@intel.com>
> Subject: [dts][PATCH V1 1/1] [next]dts/pktgen: add support pci address mapping sytle
>
>
> make pktgen trex port mapping to be compatible with pci address mapping sytle.
>
> Signed-off-by: yufengmx <yufengx.mo@intel.com>
> ---
> framework/dut.py | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/framework/dut.py b/framework/dut.py
> index fc4a2e6..c2ed0f1 100644
> --- a/framework/dut.py
> +++ b/framework/dut.py
> @@ -986,7 +986,8 @@ class Dut(Crb):
> if peer is not None:
> for remotePort in range(len(self.tester.ports_info)):
> if self.tester.ports_info[remotePort]['type'].lower() == 'trex':
> - if self.tester.ports_info[remotePort]['intf'].lower() == peer.lower():
> + if self.tester.ports_info[remotePort]['intf'].lower() == peer.lower() or \
> + self.tester.ports_info[remotePort]['pci'].lower() == peer.lower():
> hits[remotePort] = True
> self.ports_map[dutPort] = remotePort
> break
> --
> 2.21.0