* [dts][PATCH V1]tests/perf_test_base: add the correct corelist
@ 2022-05-20 1:52 Yingya Han
2022-05-25 10:27 ` Jiang, YuX
0 siblings, 1 reply; 2+ messages in thread
From: Yingya Han @ 2022-05-20 1:52 UTC (permalink / raw)
To: dts; +Cc: Yingya Han
Signed-off-by: Yingya Han <yingyax.han@intel.com>
---
tests/perf_test_base.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/perf_test_base.py b/tests/perf_test_base.py
index d60572e0..74a2a37e 100644
--- a/tests/perf_test_base.py
+++ b/tests/perf_test_base.py
@@ -1366,7 +1366,7 @@ class PerfTestBase(object):
configs.append(
[
test_item,
- _corelist,
+ corelist,
",".join(
[
"({0},{1},{2})".format(port, queue, core)
--
2.25.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* RE: [dts][PATCH V1]tests/perf_test_base: add the correct corelist
2022-05-20 1:52 [dts][PATCH V1]tests/perf_test_base: add the correct corelist Yingya Han
@ 2022-05-25 10:27 ` Jiang, YuX
0 siblings, 0 replies; 2+ messages in thread
From: Jiang, YuX @ 2022-05-25 10:27 UTC (permalink / raw)
To: Han, YingyaX, dts; +Cc: Han, YingyaX
> -----Original Message-----
> From: Yingya Han <yingyax.han@intel.com>
> Sent: Friday, May 20, 2022 9:52 AM
> To: dts@dpdk.org
> Cc: Han, YingyaX <yingyax.han@intel.com>
> Subject: [dts][PATCH V1]tests/perf_test_base: add the correct corelist
>
> Signed-off-by: Yingya Han <yingyax.han@intel.com>
> ---
Tested-by: Yu Jiang <YuX.Jiang@intel.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
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