* [dts] [PATCH V1 0/2] modify vswitch_sample_cdbma testplan and
@ 2021-09-10 8:47 Wei Ling
2021-09-10 8:59 ` Ling, WeiX
0 siblings, 1 reply; 3+ messages in thread
From: Wei Ling @ 2021-09-10 8:47 UTC (permalink / raw)
To: dts; +Cc: Wei Ling
Modify vswitch_sample_cdbma testplan and testsuite.
Wei Ling (2):
test_plans/vswitch_sample_cbdma_test_plan: modify start virtio-user
path parameter
tests/vswitch_sample_cbdma: modify testsuite code sync with testplan
update
test_plans/vswitch_sample_cbdma_test_plan.rst | 40 +++--
tests/TestSuite_vswitch_sample_cbdma.py | 166 +++++++++++-------
2 files changed, 121 insertions(+), 85 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [dts] [PATCH V1 0/2] modify vswitch_sample_cdbma testplan and
2021-09-10 8:47 [dts] [PATCH V1 0/2] modify vswitch_sample_cdbma testplan and Wei Ling
@ 2021-09-10 8:59 ` Ling, WeiX
2021-09-14 8:25 ` Wang, Yinan
0 siblings, 1 reply; 3+ messages in thread
From: Ling, WeiX @ 2021-09-10 8:59 UTC (permalink / raw)
To: dts
> -----Original Message-----
> From: Ling, WeiX <weix.ling@intel.com>
> Sent: Friday, September 10, 2021 04:48 PM
> To: dts@dpdk.org
> Cc: Ling, WeiX <weix.ling@intel.com>
> Subject: [dts][PATCH V1 0/2] modify vswitch_sample_cdbma testplan and
>
Tested-by: Wei Ling <weix.ling@intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [dts] [PATCH V1 0/2] modify vswitch_sample_cdbma testplan and
2021-09-10 8:59 ` Ling, WeiX
@ 2021-09-14 8:25 ` Wang, Yinan
0 siblings, 0 replies; 3+ messages in thread
From: Wang, Yinan @ 2021-09-14 8:25 UTC (permalink / raw)
To: Ling, WeiX, dts
Acked-by: Yinan Wang <yinan.wang@intel.com>
> -----Original Message-----
> From: dts <dts-bounces@dpdk.org> On Behalf Of Ling, WeiX
> Sent: 2021?9?10? 17:00
> To: dts@dpdk.org
> Subject: Re: [dts] [PATCH V1 0/2] modify vswitch_sample_cdbma testplan and
>
> > -----Original Message-----
> > From: Ling, WeiX <weix.ling@intel.com>
> > Sent: Friday, September 10, 2021 04:48 PM
> > To: dts@dpdk.org
> > Cc: Ling, WeiX <weix.ling@intel.com>
> > Subject: [dts][PATCH V1 0/2] modify vswitch_sample_cdbma testplan and
> >
> Tested-by: Wei Ling <weix.ling@intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-09-14 8:25 UTC | newest]
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2021-09-14 8:25 ` Wang, Yinan
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