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From: "Tu, Lijuan" <lijuan.tu@intel.com>
To: "Jiale, SongX" <songx.jiale@intel.com>, "dts@dpdk.org" <dts@dpdk.org>
Cc: "Jiale, SongX" <songx.jiale@intel.com>
Subject: RE: [dts] [PATCH V2 2/7] test_plans/vf_pmd_bonded: add test plan for vf bonding
Date: Tue, 10 Jan 2023 07:31:32 +0000	[thread overview]
Message-ID: <CY5PR11MB6187F7314F4ED00AAF14A229F5FF9@CY5PR11MB6187.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20230106093209.317472-3-songx.jiale@intel.com>

> -----Original Message-----
> From: Song Jiale <songx.jiale@intel.com>
> Sent: Friday, January 6, 2023 5:32 PM
> To: dts@dpdk.org
> Cc: Jiale, SongX <songx.jiale@intel.com>
> Subject: [dts] [PATCH V2 2/7] test_plans/vf_pmd_bonded: add test plan for vf
> bonding
> 
> add test plan for vf bonding.
> 
> Signed-off-by: Song Jiale <songx.jiale@intel.com>
> ---
>  test_plans/vf_pmd_bonded_test_plan.rst | 523 +++++++++++++++++++++++++
>  1 file changed, 523 insertions(+)
>  create mode 100644 test_plans/vf_pmd_bonded_test_plan.rst
> 
> diff --git a/test_plans/vf_pmd_bonded_test_plan.rst
> b/test_plans/vf_pmd_bonded_test_plan.rst
...
> +
> +=============
> +Bonding Tests
> +=============

The name is duplicated with pmd_bonded_test_plan.rst  and the content is highly duplicated too.

> +
> +Provide the ability to support Link Bonding for 1GbE and 10GbE ports similar

A question, Does it support 25Gbe, 40GbE, 100GbE, etc ?

...

> +
> +* NIC and IXIA ports requirements.

Can we use Trex instead of IXIA ?

> +
> +  - Tester: have 4 10Gb (82599) ports and 4 1Gb ports.
> +  - DUT: have 4 10Gb (82599) ports and 4 1Gb ports. All functional tests should
> be done on both 10G and 1G port.
> +  - IXIA: have 4 10G ports and 4 1G ports. IXIA is used for performance test.
> +
> +* BIOS settings on DUT:
> +
> +  - Enhanced Intel Speedstep----DISABLED
> +  - Processor C3--------------------DISABLED
> +  - Processor C6--------------------DISABLED
> +  - Hyper-Threading----------------ENABLED
> +  - Intel VT-d-------------------------DISABLED
> +  - MLC Streamer-------------------ENABLED
> +  - MLC Spatial Prefetcher--------ENABLED
> +  - DCU Data Prefetcher-----------ENABLED
> +  - DCU Instruction Prefetcher----ENABLED
> +  - Direct Cache Access(DCA)--------------------- ENABLED
> +  - CPU Power and Performance Policy-----------Performance
> +  - Memory Power Optimization---------------------Performance Optimized
> +  - Memory RAS and Performance Configuration-->NUMA
> + Optimized----ENABLED

The BIOS requirement is not reasonable, 
I don't think Speedstep, Hyper-Threading impact the results.

  reply	other threads:[~2023-01-10  7:31 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-06  9:32 [dts] [PATCH V2 0/7] add cases to test " Song Jiale
2023-01-06  9:32 ` [dts] [PATCH V2 1/7] tests/vf_pmd_bonded: add case " Song Jiale
2023-01-06  9:32 ` [dts] [PATCH V2 2/7] test_plans/vf_pmd_bonded: add test plan for " Song Jiale
2023-01-10  7:31   ` Tu, Lijuan [this message]
2023-01-06  9:32 ` [dts] [PATCH V2 3/7] tests/vf_pmd_bonded_8023ad: add case to test " Song Jiale
2023-01-06  9:32 ` [dts] [PATCH V2 4/7] test_plans/vf_pmd_bonded_8023ad: add test plan for " Song Jiale
2023-01-06  9:32 ` [dts] [PATCH V2 5/7] tests/vf_pmd_stacked_bonded: add cases to test " Song Jiale
2023-01-06  9:32 ` [dts] [PATCH V2 6/7] test_plans/vf_pmd_stacked_bonded: add test plan for " Song Jiale
2023-01-06  9:32 ` [dts] [PATCH V2 7/7] test_plans/index: add 3 suite Song Jiale

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