From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1E94CA00C3; Tue, 18 Jan 2022 03:01:14 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DC84A41158; Tue, 18 Jan 2022 03:01:13 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 1709740140 for ; Tue, 18 Jan 2022 03:01:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1642471273; x=1674007273; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=hgYDHFqgSz+j2C2q1DwOyNgEvO9cJlkAUKCgrS0yhmE=; b=kVxInHIrH/O6nrZ4d45+RtHVQ0vNl7jFYHwfCWUzcuWRHa1GtYeUJt/y 4LsVaHz6Faeb0/pRe4fKYUdQsFePMWfEnITFvu55NO6Hivv9+1w6YmkPc IYjgsrHAzYYxj9G5WlkWIQTPzfS7/663VVPsa29xm8BQ7pfCKjaQ2meDw MTmzDDfgV+4MbQeEv5xy3zP4LK4m5ks8b1A53J5c7TvN14jO2TBoejN6W mJe4rQtd33iMYl+Eqcs9NQ1M9LPB5S1cG01mktOWDjhqi+vQ6xydf1SFd LIlo7DAm/NCuC7SPckybNXz4yXr9PkH8MTVwVPgymSbsg4dsq2bUbnmbI A==; X-IronPort-AV: E=McAfee;i="6200,9189,10230"; a="225398540" X-IronPort-AV: E=Sophos;i="5.88,296,1635231600"; d="scan'208";a="225398540" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2022 18:01:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,296,1635231600"; d="scan'208";a="625354889" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga004.jf.intel.com with ESMTP; 17 Jan 2022 18:01:11 -0800 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Mon, 17 Jan 2022 18:01:10 -0800 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX603.ccr.corp.intel.com (10.109.6.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Tue, 18 Jan 2022 10:01:09 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2308.020; Tue, 18 Jan 2022 10:01:09 +0800 From: "Tu, Lijuan" To: "Fu, Qi" , "dts@dpdk.org" CC: "Fu, Qi" Subject: RE: [dts][PATCH V2]test_plans: add test plan for cvl 1pps Thread-Topic: [dts][PATCH V2]test_plans: add test plan for cvl 1pps Thread-Index: AQHYCRuiQEe0TBb4CEeicRgaJMypr6xoCO4g Date: Tue, 18 Jan 2022 02:01:09 +0000 Message-ID: References: <20220114162303.836537-1-qi.fu@intel.com> In-Reply-To: <20220114162303.836537-1-qi.fu@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.6.200.16 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dts-bounces@dpdk.org > -----Original Message----- > From: Qi Fu > Sent: 2022=1B$BG/=1B(B1=1B$B7n=1B(B15=1B$BF|=1B(B 0:23 > To: dts@dpdk.org > Cc: Fu, Qi > Subject: [dts][PATCH V2]test_plans: add test plan for cvl 1pps >=20 > add test plan for cvl 1pps. >=20 > Signed-off-by: Qi Fu > --- > test_plans/cvl_1pps_test_plan.rst | 165 ++++++++++++++++++++++++++++++ > test_plans/index.rst | 1 + > 2 files changed, 166 insertions(+) > create mode 100644 test_plans/cvl_1pps_test_plan.rst > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > +CVL PPS Test Plan > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PPS means packets per second, am I right? If that, "CVL 1PPS signal" is mo= re reasonable. > +Topology > +-------- > +1node+1nic+2port+fwd > +2node+1nic+1port+loopback Sorry, I can't understand the topology, could you explain more. > + when test the onboard NIC of HCC/SNR platform, the timer =3D 1, so a= ll the register need to add 4 except GLGEN_GPIO_CTL. HCC/SNR are not product names, what do they mean?