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* [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4 new cases
@ 2022-02-08  9:15 Peng Zhang
  2022-02-08  9:26 ` Fu, Qi
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Peng Zhang @ 2022-02-08  9:15 UTC (permalink / raw)
  To: dts; +Cc: qi.fu, Peng Zhang

Update script of 4 new cases according to comments and v5 test plan.

Signed-off-by: Peng Zhang <peng1x.zhang@intel.com>
---
 tests/TestSuite_cvl_1pps_signal.py | 131 +++++++++++++++++++++++++++++
 1 file changed, 131 insertions(+)
 create mode 100755 tests/TestSuite_cvl_1pps_signal.py

diff --git a/tests/TestSuite_cvl_1pps_signal.py b/tests/TestSuite_cvl_1pps_signal.py
new file mode 100755
index 00000000..4304ad64
--- /dev/null
+++ b/tests/TestSuite_cvl_1pps_signal.py
@@ -0,0 +1,131 @@
+# BSD LICENSE
+#
+# Copyright(c) 2010-2022 Intel Corporation. All rights reserved.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+#   * Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#   * Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in
+#     the documentation and/or other materials provided with the
+#     distribution.
+#   * Neither the name of Intel Corporation nor the names of its
+#     contributors may be used to endorse or promote products derived
+#     from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+import re
+from framework.pmd_output import PmdOutput
+from framework.test_case import TestCase, check_supported_nic
+
+
+class TestCVL1PPS(TestCase):
+    supported_nic = ['columbiaville_100g', 'columbiaville_25g']
+    @check_supported_nic(supported_nic)
+    def set_up_all(self):
+        """
+        Run at the start of each test suite.
+        prerequisites.
+        """
+        # Based on h/w type, chose how many ports to use
+        dut_ports = self.dut.get_ports(self.nic)
+        self.verify(len(dut_ports) >= 1, "Insufficient ports for testing")
+        # Verify that enough threads are available
+        self.cores = self.dut.get_core_list("1S/2C/1T")
+        self.verify(self.cores, "Insufficient cores for speed testing")
+        self.pci = self.dut.ports_info[dut_ports[0]]['pci']
+        self.pmd_output = PmdOutput(self.dut)
+        self.GLTSYN_AUX = re.compile(r'0x00000007\s+\(7\)')
+        self.GLTSYN_CLKO = re.compile(r'0x1DCD6500\s+\(500000000\)')
+        self.pattern = re.compile('register\s+at\s+offset\s+.*:\s+(?P<hex>0x\w+)\s+\(\d+\)')
+
+    def set_up(self):
+        """
+        Run before each test case.
+        """
+        pass
+
+    def read_register(self, addr, port_id=0):
+        cmd = 'read reg {} {}'.format(port_id, addr)
+        return self.pmd_output.execute_cmd(cmd)
+
+    def launch_testpmd(self, pin_id, rxq=4, txq=4):
+        self.out = self.pmd_output.start_testpmd(cores="1S/2C/1T", param="--rxq={} --txq={} ".format(rxq, txq),
+                                                 eal_param="-a {},pps_out='[pin:{}]'".format(self.pci, pin_id))
+        # Check the GLTSYN_AUX_OUT, GLTSYN_CLKO and other two registers
+    def check_four_registers(self, pin_id, addrs, port_id=0):
+        self.launch_testpmd(pin_id)
+        for i in range(len(addrs)):
+            out = self.read_register(addrs[i], port_id=port_id)
+            if i == 0:
+                pattern = self.GLTSYN_AUX
+            elif i == 1:
+                pattern = self.GLTSYN_CLKO
+            else:
+                pattern = self.pattern
+            res = pattern.search(out)
+            self.verify(res, 'pattern:{} not found in output info: {}'.format(pattern, out))
+            if i > 1:
+                actual_value = int(res.group('hex'), 16)
+                self.verify(actual_value != 0,
+                            'check pin id:{0} register address:{1} failed, expected value is non-zero, actual value is:{2}'.format(pin_id,addrs[i],actual_value))
+            self.logger.info('check pin id: {0} register address: {1} pass'.format(pin_id,addrs[i]))
+        # complete checking registers
+        self.quit_testpmd()
+        return res
+
+    def check_GLGEN_GPIO_CTL_value(self, hex_value, target_value):
+        self.verify(hex_value[-3] == target_value,
+                    'check register failed, target value is {} not match expected value {}'.format(hex_value[-3], target_value))
+        bit_5th = bin(int(hex_value, 16))[-5]
+        self.verify(bit_5th == '1', 'check register failed, the 5th bit is {} not match expected value {}'.format(bit_5th, 1))
+        self.logger.info('check register value {} pass'.format(hex_value))
+
+    def test_check_register_with_pin_id_0(self):
+        addrs = ['0x00088998', '0x000889B8', '0x00088928', '0x00088930', '0x000880C8']
+        res = self.check_four_registers(pin_id=0, addrs=addrs)
+        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[0] 0x000880C8 is 8. And the 5th binary digit is 1.
+        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group('hex'), target_value='8')
+
+    def test_check_register_with_pin_id_1(self):
+        addrs = ['0x000889A0', '0x000889C0', '0x00088938', '0x00088940', '0x000880CC']
+        res = self.check_four_registers(pin_id=1, addrs=addrs)
+        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[1] 0x000880CC is 9. And the 5th binary digit is 1.
+        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group('hex'), target_value='9')
+
+    def test_check_register_with_pin_id_2(self):
+        addrs = ['0x000889A8', '0x000889C8', '0x00088948', '0x00088950', '0x000880D0']
+        res = self.check_four_registers(pin_id=2, addrs=addrs)
+        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[2] 0x000880D0 is A. And the 5th binary digit is 1.
+        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group('hex'), target_value='A')
+
+    def test_check_register_with_pin_id_3(self):
+        addrs = ['0x000889B0', '0x000889D0', '0x00088958', '0x00088960', '0x000880D4']
+        res = self.check_four_registers(pin_id=3, addrs=addrs)
+        # 3rd Hexadecimal digit of GLGEN_GPIO_CTL[3] 0x000880D4 is B. And the 5th binary digit is 1.
+        self.check_GLGEN_GPIO_CTL_value(hex_value=res.group('hex'), target_value='B')
+
+    def quit_testpmd(self):
+        self.pmd_output.quit()
+
+    def tear_down(self):
+        self.dut.kill_all()
+
+    def tear_down_all(self):
+        self.dut.kill_all()
-- 
2.17.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4 new cases
  2022-02-08  9:15 [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4 new cases Peng Zhang
@ 2022-02-08  9:26 ` Fu, Qi
  2022-02-08  9:36 ` Li, WeiyuanX
  2022-02-09  1:44 ` Tu, Lijuan
  2 siblings, 0 replies; 4+ messages in thread
From: Fu, Qi @ 2022-02-08  9:26 UTC (permalink / raw)
  To: Zhang, Peng1X, dts

Acked-by: Qi Fu<qi.fu@intel.com> 

> -----Original Message-----
> From: Zhang, Peng1X <peng1x.zhang@intel.com>
> Sent: Tuesday, February 8, 2022 5:16 PM
> To: dts@dpdk.org
> Cc: Fu, Qi <qi.fu@intel.com>; Zhang, Peng1X <peng1x.zhang@intel.com>
> Subject: [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4
> new cases
> 
> Update script of 4 new cases according to comments and v5 test plan.
> 
> Signed-off-by: Peng Zhang <peng1x.zhang@intel.com>
> ---
>  tests/TestSuite_cvl_1pps_signal.py | 131 +++++++++++++++++++++++++++++
>  1 file changed, 131 insertions(+)
>  create mode 100755 tests/TestSuite_cvl_1pps_signal.py
> 
> diff --git a/tests/TestSuite_cvl_1pps_signal.py
> b/tests/TestSuite_cvl_1pps_signal.py
> new file mode 100755
> index 00000000..4304ad64
> --- /dev/null
> +++ b/tests/TestSuite_cvl_1pps_signal.py

^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4 new cases
  2022-02-08  9:15 [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4 new cases Peng Zhang
  2022-02-08  9:26 ` Fu, Qi
@ 2022-02-08  9:36 ` Li, WeiyuanX
  2022-02-09  1:44 ` Tu, Lijuan
  2 siblings, 0 replies; 4+ messages in thread
From: Li, WeiyuanX @ 2022-02-08  9:36 UTC (permalink / raw)
  To: Zhang, Peng1X, dts; +Cc: Fu, Qi, Zhang, Peng1X

[-- Attachment #1: Type: text/plain, Size: 355 bytes --]

> -----Original Message-----
> From: Peng Zhang <peng1x.zhang@intel.com>
> Sent: Tuesday, February 8, 2022 5:16 PM
> To: dts@dpdk.org
> Cc: Fu, Qi <qi.fu@intel.com>; Zhang, Peng1X <peng1x.zhang@intel.com>
> Subject: [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script
> of 4 new cases

Tested-by: Weiyuan Li <weiyuanx.li@intel.com>

[-- Attachment #2: TestCVL1PPS.log --]
[-- Type: application/octet-stream, Size: 14476 bytes --]

09/02/2022 01:59:04                            dts: 
TEST SUITE : TestCVL1PPS
09/02/2022 01:59:04                            dts: NIC :        columbiaville_25g
09/02/2022 01:59:04              dut.10.239.251.41: 
09/02/2022 01:59:04                         tester: 
09/02/2022 01:59:04                    TestCVL1PPS: Test Case test_check_register_with_pin_id_0 Begin
09/02/2022 01:59:05              dut.10.239.251.41: 
09/02/2022 01:59:05                         tester: 
09/02/2022 01:59:05              dut.10.239.251.41: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2 -n 4  --file-prefix=dpdk_4674_20220209015554  -a 0000:af:00.0,pps_out='[pin:0]' -- -i --rxq=4 --txq=4 
09/02/2022 01:59:06              dut.10.239.251.41: EAL: Detected CPU lcores: 72
EAL: Detected NUMA nodes: 2
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/dpdk_4674_20220209015554/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: 1024 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size
EAL: VFIO support initialized
EAL: Using IOMMU type 1 (Type 1)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:af:00.0 (socket 1)
ice_load_pkg_type(): Active package is: 1.3.4.0, ICE PPPoL2TPv2oUDP Package (double VLAN mode)
Interactive-mode selected
testpmd: create a new mbuf pool <mb_pool_0>: n=155456, size=2176, socket=0
testpmd: preferred mempool ops selected: ring_mp_mc
testpmd: create a new mbuf pool <mb_pool_1>: n=155456, size=2176, socket=1
testpmd: preferred mempool ops selected: ring_mp_mc

Warning! port-topology=paired and odd forward ports number, the last port will pair with itself.

Configuring Port 0 (socket 1)
ice_set_rx_function(): Using AVX2 OFFLOAD Vector Rx (port 0).
Port 0: 68:05:CA:C1:B8:C8
Checking link statuses...
Done
09/02/2022 01:59:16              dut.10.239.251.41: read reg 0 0x00088998
09/02/2022 01:59:16              dut.10.239.251.41: 
port 0 PCI register at offset 0x88998: 0x00000007 (7)
09/02/2022 01:59:16                    TestCVL1PPS: check pin id: 0 register address: 0x00088998 pass
09/02/2022 01:59:16              dut.10.239.251.41: read reg 0 0x000889B8
09/02/2022 01:59:17              dut.10.239.251.41: 
port 0 PCI register at offset 0x889B8: 0x1DCD6500 (500000000)
09/02/2022 01:59:17                    TestCVL1PPS: check pin id: 0 register address: 0x000889B8 pass
09/02/2022 01:59:17              dut.10.239.251.41: read reg 0 0x00088928
09/02/2022 01:59:17              dut.10.239.251.41: 
port 0 PCI register at offset 0x88928: 0xCC9F0AFF (3432975103)
09/02/2022 01:59:17                    TestCVL1PPS: check pin id: 0 register address: 0x00088928 pass
09/02/2022 01:59:17              dut.10.239.251.41: read reg 0 0x00088930
09/02/2022 01:59:17              dut.10.239.251.41: 
port 0 PCI register at offset 0x88930: 0x16D1C512 (382846226)
09/02/2022 01:59:17                    TestCVL1PPS: check pin id: 0 register address: 0x00088930 pass
09/02/2022 01:59:17              dut.10.239.251.41: read reg 0 0x000880C8
09/02/2022 01:59:17              dut.10.239.251.41: 
port 0 PCI register at offset 0x880C8: 0x00000817 (2071)
09/02/2022 01:59:17                    TestCVL1PPS: check pin id: 0 register address: 0x000880C8 pass
09/02/2022 01:59:17              dut.10.239.251.41: quit
09/02/2022 01:59:18              dut.10.239.251.41: 

Stopping port 0...
Stopping ports...
Done

Shutting down port 0...
Closing ports...
Port 0 is closed
Done

Bye...
09/02/2022 01:59:18                    TestCVL1PPS: check register value 0x00000817 pass
09/02/2022 01:59:18                    TestCVL1PPS: Test Case test_check_register_with_pin_id_0 Result PASSED:
09/02/2022 01:59:18              dut.10.239.251.41: kill_all: called by dut and prefix list has value.
09/02/2022 01:59:19                    TestCVL1PPS: Test Case test_check_register_with_pin_id_1 Begin
09/02/2022 01:59:19              dut.10.239.251.41:  
09/02/2022 01:59:19                         tester: 
09/02/2022 01:59:19              dut.10.239.251.41: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2 -n 4  --file-prefix=dpdk_4674_20220209015554  -a 0000:af:00.0,pps_out='[pin:1]' -- -i --rxq=4 --txq=4 
09/02/2022 01:59:21              dut.10.239.251.41: EAL: Detected CPU lcores: 72
EAL: Detected NUMA nodes: 2
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/dpdk_4674_20220209015554/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: 1024 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size
EAL: VFIO support initialized
EAL: Using IOMMU type 1 (Type 1)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:af:00.0 (socket 1)
ice_load_pkg_type(): Active package is: 1.3.4.0, ICE PPPoL2TPv2oUDP Package (double VLAN mode)
Interactive-mode selected
testpmd: create a new mbuf pool <mb_pool_0>: n=155456, size=2176, socket=0
testpmd: preferred mempool ops selected: ring_mp_mc
testpmd: create a new mbuf pool <mb_pool_1>: n=155456, size=2176, socket=1
testpmd: preferred mempool ops selected: ring_mp_mc

Warning! port-topology=paired and odd forward ports number, the last port will pair with itself.

Configuring Port 0 (socket 1)
ice_set_rx_function(): Using AVX2 OFFLOAD Vector Rx (port 0).
Port 0: 68:05:CA:C1:B8:C8
Checking link statuses...
Done
09/02/2022 01:59:31              dut.10.239.251.41: read reg 0 0x000889A0
09/02/2022 01:59:31              dut.10.239.251.41: 
port 0 PCI register at offset 0x889A0: 0x00000007 (7)
09/02/2022 01:59:31                    TestCVL1PPS: check pin id: 1 register address: 0x000889A0 pass
09/02/2022 01:59:31              dut.10.239.251.41: read reg 0 0x000889C0
09/02/2022 01:59:31              dut.10.239.251.41: 
port 0 PCI register at offset 0x889C0: 0x1DCD6500 (500000000)
09/02/2022 01:59:31                    TestCVL1PPS: check pin id: 1 register address: 0x000889C0 pass
09/02/2022 01:59:31              dut.10.239.251.41: read reg 0 0x00088938
09/02/2022 01:59:31              dut.10.239.251.41: 
port 0 PCI register at offset 0x88938: 0x0F1616FF (253105919)
09/02/2022 01:59:31                    TestCVL1PPS: check pin id: 1 register address: 0x00088938 pass
09/02/2022 01:59:31              dut.10.239.251.41: read reg 0 0x00088940
09/02/2022 01:59:31              dut.10.239.251.41: 
port 0 PCI register at offset 0x88940: 0x16D1C516 (382846230)
09/02/2022 01:59:31                    TestCVL1PPS: check pin id: 1 register address: 0x00088940 pass
09/02/2022 01:59:31              dut.10.239.251.41: read reg 0 0x000880CC
09/02/2022 01:59:31              dut.10.239.251.41: 
port 0 PCI register at offset 0x880CC: 0x00000912 (2322)
09/02/2022 01:59:31                    TestCVL1PPS: check pin id: 1 register address: 0x000880CC pass
09/02/2022 01:59:31              dut.10.239.251.41: quit
09/02/2022 01:59:32              dut.10.239.251.41: 

Stopping port 0...
Stopping ports...
Done

Shutting down port 0...
Closing ports...
Port 0 is closed
Done

Bye...
09/02/2022 01:59:32                    TestCVL1PPS: check register value 0x00000912 pass
09/02/2022 01:59:32                    TestCVL1PPS: Test Case test_check_register_with_pin_id_1 Result PASSED:
09/02/2022 01:59:32              dut.10.239.251.41: kill_all: called by dut and prefix list has value.
09/02/2022 01:59:33                    TestCVL1PPS: Test Case test_check_register_with_pin_id_2 Begin
09/02/2022 01:59:33              dut.10.239.251.41:  
09/02/2022 01:59:33                         tester: 
09/02/2022 01:59:33              dut.10.239.251.41: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2 -n 4  --file-prefix=dpdk_4674_20220209015554  -a 0000:af:00.0,pps_out='[pin:2]' -- -i --rxq=4 --txq=4 
09/02/2022 01:59:35              dut.10.239.251.41: EAL: Detected CPU lcores: 72
EAL: Detected NUMA nodes: 2
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/dpdk_4674_20220209015554/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: 1024 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size
EAL: VFIO support initialized
EAL: Using IOMMU type 1 (Type 1)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:af:00.0 (socket 1)
ice_load_pkg_type(): Active package is: 1.3.4.0, ICE PPPoL2TPv2oUDP Package (double VLAN mode)
Interactive-mode selected
testpmd: create a new mbuf pool <mb_pool_0>: n=155456, size=2176, socket=0
testpmd: preferred mempool ops selected: ring_mp_mc
testpmd: create a new mbuf pool <mb_pool_1>: n=155456, size=2176, socket=1
testpmd: preferred mempool ops selected: ring_mp_mc

Warning! port-topology=paired and odd forward ports number, the last port will pair with itself.

Configuring Port 0 (socket 1)
ice_set_rx_function(): Using AVX2 OFFLOAD Vector Rx (port 0).
Port 0: 68:05:CA:C1:B8:C8
Checking link statuses...
Done
09/02/2022 01:59:45              dut.10.239.251.41: read reg 0 0x000889A8
09/02/2022 01:59:45              dut.10.239.251.41: 
port 0 PCI register at offset 0x889A8: 0x00000007 (7)
09/02/2022 01:59:45                    TestCVL1PPS: check pin id: 2 register address: 0x000889A8 pass
09/02/2022 01:59:45              dut.10.239.251.41: read reg 0 0x000889C8
09/02/2022 01:59:45              dut.10.239.251.41: 
port 0 PCI register at offset 0x889C8: 0x1DCD6500 (500000000)
09/02/2022 01:59:45                    TestCVL1PPS: check pin id: 2 register address: 0x000889C8 pass
09/02/2022 01:59:45              dut.10.239.251.41: read reg 0 0x00088948
09/02/2022 01:59:45              dut.10.239.251.41: 
port 0 PCI register at offset 0x88948: 0x6F5A87FF (1868204031)
09/02/2022 01:59:45                    TestCVL1PPS: check pin id: 2 register address: 0x00088948 pass
09/02/2022 01:59:45              dut.10.239.251.41: read reg 0 0x00088950
09/02/2022 01:59:45              dut.10.239.251.41: 
port 0 PCI register at offset 0x88950: 0x16D1C519 (382846233)
09/02/2022 01:59:45                    TestCVL1PPS: check pin id: 2 register address: 0x00088950 pass
09/02/2022 01:59:45              dut.10.239.251.41: read reg 0 0x000880D0
09/02/2022 01:59:45              dut.10.239.251.41: 
port 0 PCI register at offset 0x880D0: 0x00000A12 (2578)
09/02/2022 01:59:45                    TestCVL1PPS: check pin id: 2 register address: 0x000880D0 pass
09/02/2022 01:59:45              dut.10.239.251.41: quit
09/02/2022 01:59:47              dut.10.239.251.41: 

Stopping port 0...
Stopping ports...
Done

Shutting down port 0...
Closing ports...
Port 0 is closed
Done

Bye...
09/02/2022 01:59:47                    TestCVL1PPS: check register value 0x00000A12 pass
09/02/2022 01:59:47                    TestCVL1PPS: Test Case test_check_register_with_pin_id_2 Result PASSED:
09/02/2022 01:59:47              dut.10.239.251.41: kill_all: called by dut and prefix list has value.
09/02/2022 01:59:47                    TestCVL1PPS: Test Case test_check_register_with_pin_id_3 Begin
09/02/2022 01:59:47              dut.10.239.251.41:  
09/02/2022 01:59:47                         tester: 
09/02/2022 01:59:47              dut.10.239.251.41: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2 -n 4  --file-prefix=dpdk_4674_20220209015554  -a 0000:af:00.0,pps_out='[pin:3]' -- -i --rxq=4 --txq=4 
09/02/2022 01:59:49              dut.10.239.251.41: EAL: Detected CPU lcores: 72
EAL: Detected NUMA nodes: 2
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/dpdk_4674_20220209015554/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: 1024 hugepages of size 2097152 reserved, but no mounted hugetlbfs found for that size
EAL: VFIO support initialized
EAL: Using IOMMU type 1 (Type 1)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:af:00.0 (socket 1)
ice_load_pkg_type(): Active package is: 1.3.4.0, ICE PPPoL2TPv2oUDP Package (double VLAN mode)
Interactive-mode selected
testpmd: create a new mbuf pool <mb_pool_0>: n=155456, size=2176, socket=0
testpmd: preferred mempool ops selected: ring_mp_mc
testpmd: create a new mbuf pool <mb_pool_1>: n=155456, size=2176, socket=1
testpmd: preferred mempool ops selected: ring_mp_mc

Warning! port-topology=paired and odd forward ports number, the last port will pair with itself.

Configuring Port 0 (socket 1)
ice_set_rx_function(): Using AVX2 OFFLOAD Vector Rx (port 0).
Port 0: 68:05:CA:C1:B8:C8
Checking link statuses...
Done
09/02/2022 01:59:59              dut.10.239.251.41: read reg 0 0x000889B0
09/02/2022 01:59:59              dut.10.239.251.41: 
port 0 PCI register at offset 0x889B0: 0x00000007 (7)
09/02/2022 01:59:59                    TestCVL1PPS: check pin id: 3 register address: 0x000889B0 pass
09/02/2022 01:59:59              dut.10.239.251.41: read reg 0 0x000889D0
09/02/2022 01:59:59              dut.10.239.251.41: 
port 0 PCI register at offset 0x889D0: 0x1DCD6500 (500000000)
09/02/2022 01:59:59                    TestCVL1PPS: check pin id: 3 register address: 0x000889D0 pass
09/02/2022 01:59:59              dut.10.239.251.41: read reg 0 0x00088958
09/02/2022 01:59:59              dut.10.239.251.41: 
port 0 PCI register at offset 0x88958: 0xCF9EF8FF (3483302143)
09/02/2022 01:59:59                    TestCVL1PPS: check pin id: 3 register address: 0x00088958 pass
09/02/2022 01:59:59              dut.10.239.251.41: read reg 0 0x00088960
09/02/2022 01:59:59              dut.10.239.251.41: 
port 0 PCI register at offset 0x88960: 0x16D1C51C (382846236)
09/02/2022 01:59:59                    TestCVL1PPS: check pin id: 3 register address: 0x00088960 pass
09/02/2022 01:59:59              dut.10.239.251.41: read reg 0 0x000880D4
09/02/2022 02:00:00              dut.10.239.251.41: 
port 0 PCI register at offset 0x880D4: 0x00000B17 (2839)
09/02/2022 02:00:00                    TestCVL1PPS: check pin id: 3 register address: 0x000880D4 pass
09/02/2022 02:00:00              dut.10.239.251.41: quit
09/02/2022 02:00:01              dut.10.239.251.41: 

Stopping port 0...
Stopping ports...
Done

Shutting down port 0...
Closing ports...
Port 0 is closed
Done

Bye...
09/02/2022 02:00:01                    TestCVL1PPS: check register value 0x00000B17 pass
09/02/2022 02:00:01                    TestCVL1PPS: Test Case test_check_register_with_pin_id_3 Result PASSED:
09/02/2022 02:00:01              dut.10.239.251.41: kill_all: called by dut and prefix list has value.
09/02/2022 02:00:01                            dts: 
TEST SUITE ENDED: TestCVL1PPS

^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4 new cases
  2022-02-08  9:15 [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4 new cases Peng Zhang
  2022-02-08  9:26 ` Fu, Qi
  2022-02-08  9:36 ` Li, WeiyuanX
@ 2022-02-09  1:44 ` Tu, Lijuan
  2 siblings, 0 replies; 4+ messages in thread
From: Tu, Lijuan @ 2022-02-09  1:44 UTC (permalink / raw)
  To: Zhang, Peng1X, dts; +Cc: Fu, Qi, Zhang, Peng1X

> -----Original Message-----
> From: Peng Zhang <peng1x.zhang@intel.com>
> Sent: 2022年2月8日 17:16
> To: dts@dpdk.org
> Cc: Fu, Qi <qi.fu@intel.com>; Zhang, Peng1X <peng1x.zhang@intel.com>
> Subject: [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4
> new cases
> 
> Update script of 4 new cases according to comments and v5 test plan.
> 
> Signed-off-by: Peng Zhang <peng1x.zhang@intel.com>

Applied with commit message changed.

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2022-02-09  1:44 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-08  9:15 [dts][PATCH V2] /tests/TestSuite_cvl_1pps_signal.py update script of 4 new cases Peng Zhang
2022-02-08  9:26 ` Fu, Qi
2022-02-08  9:36 ` Li, WeiyuanX
2022-02-09  1:44 ` Tu, Lijuan

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