From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail04.ics.ntt-tx.co.jp (mail05.ics.ntt-tx.co.jp [210.232.35.69]) by dpdk.org (Postfix) with ESMTP id 107A82A66 for ; Thu, 28 Dec 2017 05:56:07 +0100 (CET) Received: from gwchk03.silk.ntt-tx.co.jp (gwchk03.silk.ntt-tx.co.jp [10.107.0.111]) by mail04.ics.ntt-tx.co.jp (unknown) with ESMTP id vBS4u6tT025082 for unknown; Thu, 28 Dec 2017 13:56:06 +0900 Received: (from root@localhost) by gwchk03.silk.ntt-tx.co.jp (unknown) id vBS4u5LJ027192 for unknown; Thu, 28 Dec 2017 13:56:05 +0900 Received: from gwchk.silk.ntt-tx.co.jp [10.107.0.110] by gwchk03.silk.ntt-tx.co.jp with ESMTP id PAA27180; Thu, 28 Dec 2017 13:56:05 +0900 Received: from imss03.silk.ntt-tx.co.jp (localhost [127.0.0.1]) by imss03.silk.ntt-tx.co.jp (unknown) with ESMTP id vBS4u4K4010915 for unknown; Thu, 28 Dec 2017 13:56:04 +0900 Received: from mgate01.silk.ntt-tx.co.jp (smtp02.silk.ntt-tx.co.jp [10.107.0.37]) by imss03.silk.ntt-tx.co.jp (unknown) with ESMTP id vBS4u4sc010910 for unknown; Thu, 28 Dec 2017 13:56:04 +0900 Message-Id: <201712280456.vBS4u4sc010910@imss03.silk.ntt-tx.co.jp> Received: from localhost by mgate01.silk.ntt-tx.co.jp (unknown) id vBS4u4ab025622 ; Thu, 28 Dec 2017 13:56:04 +0900 From: x-fn-spp@sl.ntt-tx.co.jp To: spp@dpdk.org Date: Thu, 28 Dec 2017 13:55:10 +0900 X-Mailer: git-send-email 1.9.1 In-Reply-To: <4aae78ff-3b6c-cdfe-a8b7-24ec08b73935@lab.ntt.co.jp> References: <4aae78ff-3b6c-cdfe-a8b7-24ec08b73935@lab.ntt.co.jp> X-TM-AS-MML: No Subject: [spp] [PATCH 03/57] spp_vf: comment out check of using cores X-BeenThere: spp@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Soft Patch Panel List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Dec 2017 04:56:09 -0000 From: Hiroyuki Nakamura Bug workaround. Current implementation prevent use of over 32 cores due to int type restriction. Signed-off-by: Daiki Yamashita Signed-off-by: Yasufum Ogawa --- src/vf/spp_vf.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/vf/spp_vf.c b/src/vf/spp_vf.c index f035d07..830aaaa 100644 --- a/src/vf/spp_vf.c +++ b/src/vf/spp_vf.c @@ -468,12 +468,14 @@ set_form_proc_info(struct spp_config_area *config) } } +#if 0 /* bugfix#385 */ if (unlikely((cpu_bit & g_startup_param.cpu) != cpu_bit)) { /* CPU mismatch */ RTE_LOG(ERR, APP, "CPU mismatch (cpu param = %lx, config = %lx)\n", g_startup_param.cpu, cpu_bit); return -1; } +#endif return 0; } -- 1.9.1