[PATCH 3/7] net/txgbe: fix register polling

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* [PATCH 3/7] net/txgbe: fix register polling
       [not found] <20220620075512.588744-1-jiawenwu@trustnetic.com>
@ 2022-06-20  7:55 ` Jiawen Wu
  2022-06-21 12:19   ` Ferruh Yigit
  2022-06-20  7:55 ` [PATCH 4/7] net/ngbe: add more packet statistics Jiawen Wu
  2022-06-20  7:55 ` [PATCH 5/7] net/ngbe: fix YT PHY UTP mode to link up Jiawen Wu
  2 siblings, 1 reply; 5+ messages in thread
From: Jiawen Wu @ 2022-06-20  7:55 UTC (permalink / raw)
  To: dev; +Cc: Jiawen Wu, stable

Fix to poll some specific registers, which expect bit 0.

Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 3139796911..911bb6e04e 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,
 	}
 
 	do {
-		all |= rd32(hw, reg);
-		value |= mask & all;
+		if (expect != 0) {
+			all |= rd32(hw, reg);
+			value |= mask & all;
+		} else {
+			all = rd32(hw, reg);
+			value = mask & all;
+		}
 		if (value == expect)
 			break;
 
@@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,
 
 #define wr32w(hw, reg, val, mask, slice) do { \
 	wr32((hw), reg, val); \
-	po32m((hw), reg, mask, mask, NULL, 5, slice); \
+	po32m((hw), reg, mask, 0, NULL, 5, slice); \
 } while (0)
 
 #define TXGBE_XPCS_IDAADDR    0x13000
-- 
2.27.0




^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 3/7] net/txgbe: fix register polling
  2022-06-20  7:55 ` [PATCH 3/7] net/txgbe: fix register polling Jiawen Wu
@ 2022-06-21 12:19   ` Ferruh Yigit
  2022-06-22  2:44     ` Jiawen Wu
  0 siblings, 1 reply; 5+ messages in thread
From: Ferruh Yigit @ 2022-06-21 12:19 UTC (permalink / raw)
  To: Jiawen Wu; +Cc: stable, dev

On 6/20/2022 8:55 AM, Jiawen Wu wrote:
> Fix to poll some specific registers, which expect bit 0.
> 
> Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
> ---
>   drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++---
>   1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
> index 3139796911..911bb6e04e 100644
> --- a/drivers/net/txgbe/base/txgbe_regs.h
> +++ b/drivers/net/txgbe/base/txgbe_regs.h
> @@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,
>   	}
>   
>   	do {
> -		all |= rd32(hw, reg);
> -		value |= mask & all;
> +		if (expect != 0) {
> +			all |= rd32(hw, reg);
> +			value |= mask & all;
> +		} else {
> +			all = rd32(hw, reg);
> +			value = mask & all;
> +		}
>   		if (value == expect)
>   			break;
>   
> @@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,
>   
>   #define wr32w(hw, reg, val, mask, slice) do { \
>   	wr32((hw), reg, val); \
> -	po32m((hw), reg, mask, mask, NULL, 5, slice); \
> +	po32m((hw), reg, mask, 0, NULL, 5, slice); \

Just to double check, is this change intentional, to always expect 
reading '0' from registers after writing to them?

Perhaps you can explain a little more about this polling after 
read/write logic and what was wrong in the commit log.

>   } while (0)
>   
>   #define TXGBE_XPCS_IDAADDR    0x13000


^ permalink raw reply	[flat|nested] 5+ messages in thread

* RE: [PATCH 3/7] net/txgbe: fix register polling
  2022-06-21 12:19   ` Ferruh Yigit
@ 2022-06-22  2:44     ` Jiawen Wu
  0 siblings, 0 replies; 5+ messages in thread
From: Jiawen Wu @ 2022-06-22  2:44 UTC (permalink / raw)
  To: 'Ferruh Yigit'; +Cc: stable, dev

On Tuesday, June 21, 2022 8:19 PM, Ferruh Yigit wrote:
> On 6/20/2022 8:55 AM, Jiawen Wu wrote:
> > Fix to poll some specific registers, which expect bit 0.
> >
> > Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
> > ---
> >   drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++---
> >   1 file changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/net/txgbe/base/txgbe_regs.h
> > b/drivers/net/txgbe/base/txgbe_regs.h
> > index 3139796911..911bb6e04e 100644
> > --- a/drivers/net/txgbe/base/txgbe_regs.h
> > +++ b/drivers/net/txgbe/base/txgbe_regs.h
> > @@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask,
> u32 expect, u32 *actual,
> >   	}
> >
> >   	do {
> > -		all |= rd32(hw, reg);
> > -		value |= mask & all;
> > +		if (expect != 0) {
> > +			all |= rd32(hw, reg);
> > +			value |= mask & all;
> > +		} else {
> > +			all = rd32(hw, reg);
> > +			value = mask & all;
> > +		}
> >   		if (value == expect)
> >   			break;
> >
> > @@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask,
> > u32 expect, u32 *actual,
> >
> >   #define wr32w(hw, reg, val, mask, slice) do { \
> >   	wr32((hw), reg, val); \
> > -	po32m((hw), reg, mask, mask, NULL, 5, slice); \
> > +	po32m((hw), reg, mask, 0, NULL, 5, slice); \
> 
> Just to double check, is this change intentional, to always expect reading '0'
> from registers after writing to them?
> 
> Perhaps you can explain a little more about this polling after read/write logic
> and what was wrong in the commit log.
> 

This is exactly what register expects. 'wr32w' is used for IPsec Rx Index register.
For this register, when write command bit set, the content of register affected, and immediately self cleared by hardware.
So it always expect reading '0' from register mask 'TXGBE_IPSRXIDX_WRITE'.

> >   } while (0)
> >
> >   #define TXGBE_XPCS_IDAADDR    0x13000





^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 4/7] net/ngbe: add more packet statistics
       [not found] <20220620075512.588744-1-jiawenwu@trustnetic.com>
  2022-06-20  7:55 ` [PATCH 3/7] net/txgbe: fix register polling Jiawen Wu
@ 2022-06-20  7:55 ` Jiawen Wu
  2022-06-20  7:55 ` [PATCH 5/7] net/ngbe: fix YT PHY UTP mode to link up Jiawen Wu
  2 siblings, 0 replies; 5+ messages in thread
From: Jiawen Wu @ 2022-06-20  7:55 UTC (permalink / raw)
  To: dev; +Cc: Jiawen Wu, stable

Add more hardware extended statistics.

Fixes: 8b433d04adc9 ("net/ngbe: support device xstats")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/ngbe_ethdev.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c
index c4216f7e34..33a2f335e1 100644
--- a/drivers/net/ngbe/ngbe_ethdev.c
+++ b/drivers/net/ngbe/ngbe_ethdev.c
@@ -164,6 +164,8 @@ static const struct rte_ngbe_xstats_name_off rte_ngbe_stats_strings[] = {
 	HW_XSTAT(rx_management_packets),
 	HW_XSTAT(tx_management_packets),
 	HW_XSTAT(rx_management_dropped),
+	HW_XSTAT(rx_dma_drop),
+	HW_XSTAT(tx_secdrp_packets),
 
 	/* Basic Error */
 	HW_XSTAT(rx_crc_errors),
@@ -179,6 +181,12 @@ static const struct rte_ngbe_xstats_name_off rte_ngbe_stats_strings[] = {
 	HW_XSTAT(mac_local_errors),
 	HW_XSTAT(mac_remote_errors),
 
+	/* PB Stats */
+	HW_XSTAT(rx_up_dropped),
+	HW_XSTAT(rdb_pkt_cnt),
+	HW_XSTAT(rdb_repli_cnt),
+	HW_XSTAT(rdb_drp_cnt),
+
 	/* MACSEC */
 	HW_XSTAT(tx_macsec_pkts_untagged),
 	HW_XSTAT(tx_macsec_pkts_encrypted),
-- 
2.27.0




^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 5/7] net/ngbe: fix YT PHY UTP mode to link up
       [not found] <20220620075512.588744-1-jiawenwu@trustnetic.com>
  2022-06-20  7:55 ` [PATCH 3/7] net/txgbe: fix register polling Jiawen Wu
  2022-06-20  7:55 ` [PATCH 4/7] net/ngbe: add more packet statistics Jiawen Wu
@ 2022-06-20  7:55 ` Jiawen Wu
  2 siblings, 0 replies; 5+ messages in thread
From: Jiawen Wu @ 2022-06-20  7:55 UTC (permalink / raw)
  To: dev; +Cc: Jiawen Wu, stable

Fix to read and write the correct register fields for yt8521s and
yt8531s PHY, since mode check was added.

Fixes: 1c44384fce76 ("net/ngbe: support custom PHY interfaces")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/base/ngbe_phy_yt.c | 42 ++++++++++++++---------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c
index f46121b8d1..9dd2b2264f 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.c
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c
@@ -146,21 +146,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 			}
 			/* duplex full */
 			value |= YT_BCR_DUPLEX | YT_BCR_RESET;
-			hw->phy.write_reg(hw, YT_BCR, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
 
 			goto skip_an;
 		}
 
 		/*disable 100/10base-T Self-negotiation ability*/
-		hw->phy.read_reg(hw, YT_ANA, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
 		value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |
 			YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);
-		hw->phy.write_reg(hw, YT_ANA, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
 
 		/*disable 1000base-T Self-negotiation ability*/
-		hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
 		value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);
-		hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
 
 		if (speed & NGBE_LINK_SPEED_1GB_FULL) {
 			hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
@@ -176,19 +176,19 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 		}
 
 		/* enable 1000base-T Self-negotiation ability */
-		hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
 		value |= value_r9;
-		hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
 
 		/* enable 100/10base-T Self-negotiation ability */
-		hw->phy.read_reg(hw, YT_ANA, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
 		value |= value_r4;
-		hw->phy.write_reg(hw, YT_ANA, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
 
 		/* software reset to make the above configuration take effect*/
-		hw->phy.read_reg(hw, YT_BCR, 0, &value);
+		ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
 		value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;
-		hw->phy.write_reg(hw, YT_BCR, 0, value);
+		ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
 skip_an:
 		hw->phy.set_phy_power(hw, true);
 	} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) {
@@ -219,15 +219,15 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 		} else {
 			/* utp up */
 			/*disable 100/10base-T Self-negotiation ability*/
-			hw->phy.read_reg(hw, YT_ANA, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
 			value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF |
 				YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF);
-			hw->phy.write_reg(hw, YT_ANA, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
 
 			/*disable 1000base-T Self-negotiation ability*/
-			hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
 			value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF);
-			hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
 
 			if (speed & NGBE_LINK_SPEED_1GB_FULL) {
 				hw->phy.autoneg_advertised |=
@@ -246,21 +246,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 			}
 
 			/* enable 1000base-T Self-negotiation ability */
-			hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value);
 			value |= value_r9;
-			hw->phy.write_reg(hw, YT_MS_CTRL, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value);
 
 			/* enable 100/10base-T Self-negotiation ability */
-			hw->phy.read_reg(hw, YT_ANA, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value);
 			value |= value_r4;
-			hw->phy.write_reg(hw, YT_ANA, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value);
 
 			/* software reset to make the above configuration
 			 * take effect
 			 */
-			hw->phy.read_reg(hw, YT_BCR, 0, &value);
+			ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
 			value |= YT_BCR_RESET;
-			hw->phy.write_reg(hw, YT_BCR, 0, value);
+			ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
 		}
 	} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) {
 		hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
-- 
2.27.0




^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2022-06-22  2:44 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <20220620075512.588744-1-jiawenwu@trustnetic.com>
2022-06-20  7:55 ` [PATCH 3/7] net/txgbe: fix register polling Jiawen Wu
2022-06-21 12:19   ` Ferruh Yigit
2022-06-22  2:44     ` Jiawen Wu
2022-06-20  7:55 ` [PATCH 4/7] net/ngbe: add more packet statistics Jiawen Wu
2022-06-20  7:55 ` [PATCH 5/7] net/ngbe: fix YT PHY UTP mode to link up Jiawen Wu

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