From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3D8A4A09EF for ; Tue, 22 Dec 2020 07:51:17 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 073F9CAAD; Tue, 22 Dec 2020 07:51:16 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 22F64CA74; Tue, 22 Dec 2020 07:51:10 +0100 (CET) IronPort-SDR: IpwlUJ8+0RbBLvSAUhOSQQlIdVGayrkrD8gpAUFbu6AQPtvJ/OE4wyebUludw+69v19QM1brE9 ghHGHDoFYL5w== X-IronPort-AV: E=McAfee;i="6000,8403,9842"; a="239914435" X-IronPort-AV: E=Sophos;i="5.78,438,1599548400"; d="scan'208";a="239914435" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2020 22:51:08 -0800 IronPort-SDR: BNE2ZUTXBp76CehzvQ6O0zBJj02uPRmU0swShOQHIbOqEJNeK5WfH92f3Qx5Lz31OaSIyel7cs RY0S+NKk8VDw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,438,1599548400"; d="scan'208";a="345426212" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by orsmga006.jf.intel.com with ESMTP; 21 Dec 2020 22:51:08 -0800 Received: from shsmsx604.ccr.corp.intel.com (10.109.6.214) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 21 Dec 2020 22:51:07 -0800 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by SHSMSX604.ccr.corp.intel.com (10.109.6.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 22 Dec 2020 14:51:05 +0800 Received: from shsmsx606.ccr.corp.intel.com ([10.109.6.216]) by SHSMSX606.ccr.corp.intel.com ([10.109.6.216]) with mapi id 15.01.1713.004; Tue, 22 Dec 2020 14:51:05 +0800 From: "Zhou, JunX W" To: "Yu, DapengX" , "Guo, Jia" CC: "dev@dpdk.org" , "Yu, DapengX" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] net/ixgbe: fix fdirctrl register setting Thread-Index: AQHW0srBkOrJvfI17U6zm2c4Z3Y/dqoCt+ew Date: Tue, 22 Dec 2020 06:51:05 +0000 Message-ID: <09872e2e27dc485aa2e24593002eaf9f@intel.com> References: <20201211013506.49885-1-dapengx.yu@intel.com> <20201215101031.99657-1-dapengx.yu@intel.com> In-Reply-To: <20201215101031.99657-1-dapengx.yu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH v2] net/ixgbe: fix fdirctrl register setting X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Tested-by: Zhou, Jun =20 -----Original Message----- From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of dapengx.yu@intel.com Sent: Tuesday, December 15, 2020 6:11 PM To: Guo, Jia Cc: dev@dpdk.org; Yu, DapengX ; stable@dpdk.org Subject: [dpdk-dev] [PATCH v2] net/ixgbe: fix fdirctrl register setting From: YU DAPENG The function ixgbe_fdir_set_flexbytes_offset is used when create FDir rule = for flexbytes. It set a register: FDIRCTRL.FLEX_OFFSET, which cause that ev= en if the FDir flexbytes rule is destroyed, the rule still direct the packe= t and transfer it to the wrong place. It is because setting FDIRCTRL shall = only be permitted on Flow Director initialization flow or clearing the Flow= Director table according to intel datasheet, otherwise unexpected happens.= In order to evade the limit, add code to set FDIRCMD.CLEARHT to 1b and the= n clear it back to 0b to make the setting act like the Flow Director initia= lization flow or clearing the Flow Director table. Fixes: f35fec63dde1 ("net/ixgbe: enable flex bytes for generic flow API") Cc: stable@dpdk.org Signed-off-by: YU DAPENG --- drivers/net/ixgbe/ixgbe_fdir.c | 29 +++++++++++++++++++++++++++++ drivers= /net/ixgbe/ixgbe_flow.c | 15 ++++++++------- 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_fdir.c b/drivers/net/ixgbe/ixgbe_fdir.= c index a0fab5070..11b9effeb 100644 --- a/drivers/net/ixgbe/ixgbe_fdir.c +++ b/drivers/net/ixgbe/ixgbe_fdir.c @@ -503,9 +503,30 @@ ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *de= v, uint16_t offset) { struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct ixgbe_hw_fdir_info *fdir_info =3D + IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private); uint32_t fdirctrl; int i; =20 + if (fdir_info->flex_bytes_offset =3D=3D offset) + return 0; + + /** + * 82599 adapters flow director init flow cannot be restarted, + * Workaround 82599 silicon errata by performing the following steps + * before re-writing the FDIRCTRL control register with the same value. + * - write 1 to bit 8 of FDIRCMD register & + * - write 0 to bit 8 of FDIRCMD register + */ + IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, + (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | + IXGBE_FDIRCMD_CLEARHT)); + IXGBE_WRITE_FLUSH(hw); + IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, + (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & + ~IXGBE_FDIRCMD_CLEARHT)); + IXGBE_WRITE_FLUSH(hw); + fdirctrl =3D IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); =20 fdirctrl &=3D ~IXGBE_FDIRCTRL_FLEX_MASK; @@ -520,6 +541,14 @@ ixgbe_fdir_= set_flexbytes_offset(struct rte_eth_dev *dev, break; msec_delay(1); } + + if (i >=3D IXGBE_FDIR_INIT_DONE_POLL) { + PMD_DRV_LOG(ERR, "Flow Director poll time exceeded!"); + return -ETIMEDOUT; + } + + fdir_info->flex_bytes_offset =3D offset; + return 0; } =20 diff --git a/drivers/net/ixgbe/ixgbe_flow.c b/drivers/net/ixgbe/ixgbe_flow.= c index 39f6ed73f..9aeb2e4a4 100644 --- a/drivers/net/ixgbe/ixgbe_flow.c +++ b/drivers/net/ixgbe/ixgbe_flow.c @@ -3137,13 +3137,13 @@ ixgbe_flow_create(struct rte_eth_dev *dev, rte_memcpy(&fdir_info->mask, &fdir_rule.mask, sizeof(struct ixgbe_hw_fdir_mask)); - fdir_info->flex_bytes_offset =3D - fdir_rule.flex_bytes_offset; =20 - if (fdir_rule.mask.flex_bytes_mask) - ixgbe_fdir_set_flexbytes_offset(dev, + if (fdir_rule.mask.flex_bytes_mask) { + ret =3D ixgbe_fdir_set_flexbytes_offset(dev, fdir_rule.flex_bytes_offset); - + if (ret) + goto out; + } ret =3D ixgbe_fdir_set_input_mask(dev); if (ret) goto out; @@ -3161,8 +3161,9 @@ ixgbe_flow_create(struct rte_eth_dev *dev, if (ret) goto out; =20 - if (fdir_info->flex_bytes_offset !=3D - fdir_rule.flex_bytes_offset) + if (fdir_rule.mask.flex_bytes_mask && + fdir_info->flex_bytes_offset !=3D + fdir_rule.flex_bytes_offset) goto out; } } -- 2.26.2.windows.1