From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 9867910BF6; Wed, 21 Dec 2016 10:52:04 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 21 Dec 2016 01:52:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,382,1477983600"; d="scan'208";a="1084967473" Received: from dpdk4.bj.intel.com ([172.16.182.178]) by fmsmga001.fm.intel.com with ESMTP; 21 Dec 2016 01:52:03 -0800 From: Wei Dai To: dev@dpdk.org Cc: helin.zhang@intel.com, konstantin.ananyev@intel.com, Wei Dai , stable@dpdk.org Date: Wed, 21 Dec 2016 17:47:56 +0800 Message-Id: <1482313694-31602-13-git-send-email-wei.dai@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1482313694-31602-1-git-send-email-wei.dai@intel.com> References: <1482313694-31602-1-git-send-email-wei.dai@intel.com> Subject: [dpdk-stable] [PATCH v2 12/30] net/ixgbe/base: fix SGMII link setup for M88 PHYs X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Dec 2016 09:52:05 -0000 Fix ixgbe_setup_sgmii_m88 to set lane speed to autoneg instead of 1G to prevent problems with link between PHYs Fixes: d4b4c6845487 ("net/ixgbe/base: add X550em_a FW ALEF support") CC: stable@dpdk.org Signed-off-by: Wei Dai --- drivers/net/ixgbe/base/ixgbe_x550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c index d5dffdf..5cf9e40 100644 --- a/drivers/net/ixgbe/base/ixgbe_x550.c +++ b/drivers/net/ixgbe/base/ixgbe_x550.c @@ -1778,7 +1778,7 @@ STATIC s32 ixgbe_setup_sgmii_m88(struct ixgbe_hw *hw, ixgbe_link_speed speed, return rc; flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; - flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; + flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; -- 2.7.4