From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id B69C116E for ; Thu, 25 May 2017 11:51:30 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 May 2017 02:51:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,391,1491289200"; d="scan'208";a="91624453" Received: from yliu-dev.sh.intel.com ([10.239.67.162]) by orsmga002.jf.intel.com with ESMTP; 25 May 2017 02:51:29 -0700 From: Yuanhan Liu To: Jerin Jacob Cc: Yuanhan Liu , Thomas Monjalon , dpdk stable Date: Thu, 25 May 2017 17:48:50 +0800 Message-Id: <1495705809-21416-78-git-send-email-yuanhan.liu@linux.intel.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1495705809-21416-1-git-send-email-yuanhan.liu@linux.intel.com> References: <1495705809-21416-1-git-send-email-yuanhan.liu@linux.intel.com> Subject: [dpdk-stable] patch 'net/thunderx: use internal byte ordering macros' has been queued to stable release 17.02.1 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 May 2017 09:51:31 -0000 Hi, FYI, your patch has been queued to stable release 17.02.1 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/28/17. So please shout if anyone has objections. Thanks. --yliu --- >>From 5cef256956ffa66c73b5d48a99975ea6021cf198 Mon Sep 17 00:00:00 2001 From: Jerin Jacob Date: Tue, 11 Apr 2017 01:14:34 +0530 Subject: [PATCH] net/thunderx: use internal byte ordering macros [ upstream commit 5ba411079ffdfb58906d40bb349c19d18c12a3ba ] The base code was using native GCC macros for endian detection. Change to portable rte_byteorder.h based endian detection. Fixes: 262d43fe20ee ("net/thunderx/base: add HW register definitions") Suggested-by: Thomas Monjalon Signed-off-by: Jerin Jacob --- drivers/net/thunderx/base/nicvf_hw_defs.h | 58 +++++++++++++++---------------- drivers/net/thunderx/base/nicvf_mbox.c | 2 +- drivers/net/thunderx/base/nicvf_plat.h | 4 +++ 3 files changed, 33 insertions(+), 31 deletions(-) diff --git a/drivers/net/thunderx/base/nicvf_hw_defs.h b/drivers/net/thunderx/base/nicvf_hw_defs.h index 00dd2fe..79f83c8 100644 --- a/drivers/net/thunderx/base/nicvf_hw_defs.h +++ b/drivers/net/thunderx/base/nicvf_hw_defs.h @@ -36,6 +36,8 @@ #include #include +#include "nicvf_plat.h" + /* Virtual function register offsets */ #define NIC_VF_CFG (0x000020) @@ -213,10 +215,6 @@ typedef uint64_t nicvf_phys_addr_t; -#ifndef __BYTE_ORDER__ -#error __BYTE_ORDER__ not defined -#endif - /* vNIC HW Enumerations */ enum nic_send_ld_type_e { @@ -559,7 +557,7 @@ enum nic_stat_vnic_tx_e { typedef union { uint64_t u64; struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t cqe_type:4; uint64_t stdn_fault:1; uint64_t rsvd0:1; @@ -604,7 +602,7 @@ typedef union { typedef union { uint64_t u64; struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t pkt_len:16; uint64_t l2_ptr:8; uint64_t l3_ptr:8; @@ -629,7 +627,7 @@ typedef union { typedef union { uint64_t u64; struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t rss_tag:32; uint64_t vlan_tci:16; uint64_t vlan_ptr:8; @@ -646,7 +644,7 @@ typedef union { typedef union { uint64_t u64; struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint16_t rb3_sz; uint16_t rb2_sz; uint16_t rb1_sz; @@ -663,7 +661,7 @@ typedef union { typedef union { uint64_t u64; struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint16_t rb7_sz; uint16_t rb6_sz; uint16_t rb5_sz; @@ -680,7 +678,7 @@ typedef union { typedef union { uint64_t u64; struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint16_t rb11_sz; uint16_t rb10_sz; uint16_t rb9_sz; @@ -697,7 +695,7 @@ typedef union { typedef union { uint64_t u64; struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t vlan_found:1; uint64_t vlan_stripped:1; uint64_t vlan2_found:1; @@ -742,7 +740,7 @@ struct cqe_rx_t { }; struct cqe_rx_tcp_err_t { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t cqe_type:4; /* W0 */ uint64_t rsvd0:60; @@ -764,7 +762,7 @@ struct cqe_rx_tcp_err_t { }; struct cqe_rx_tcp_t { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t cqe_type:4; /* W0 */ uint64_t rsvd0:52; uint64_t cq_tcp_status:8; @@ -786,7 +784,7 @@ struct cqe_rx_tcp_t { }; struct cqe_send_t { -#if defined(__BIG_ENDIAN_BITFIELD) +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t cqe_type:4; /* W0 */ uint64_t rsvd0:4; uint64_t sqe_ptr:16; @@ -798,7 +796,7 @@ struct cqe_send_t { uint64_t send_status:8; uint64_t ptp_timestamp:64; /* W1 */ -#elif defined(__LITTLE_ENDIAN_BITFIELD) +#elif NICVF_BYTE_ORDER == NICVF_LITTLE_ENDIAN uint64_t send_status:8; uint64_t rsvd3:8; uint64_t sq_idx:3; @@ -814,7 +812,7 @@ struct cqe_send_t { }; struct cq_entry_type_t { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t cqe_type:4; uint64_t __pad:60; #else @@ -835,7 +833,7 @@ union cq_entry_t { NICVF_STATIC_ASSERT(sizeof(union cq_entry_t) == 512); struct rbdr_entry_t { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN union { struct { uint64_t rsvd0:15; @@ -860,7 +858,7 @@ NICVF_STATIC_ASSERT(sizeof(struct rbdr_entry_t) == sizeof(uint64_t)); /* TCP reassembly context */ struct rbe_tcp_cnxt_t { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t tcp_pkt_cnt:12; uint64_t rsvd1:4; uint64_t align_hdr_bytes:4; @@ -899,7 +897,7 @@ struct rx_hdr_t { }; struct sq_crc_subdesc { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t rsvd1:32; uint64_t crc_ival:32; uint64_t subdesc_type:4; @@ -921,7 +919,7 @@ struct sq_crc_subdesc { }; struct sq_gather_subdesc { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t subdesc_type:4; /* W0 */ uint64_t ld_type:2; uint64_t rsvd0:42; @@ -942,7 +940,7 @@ struct sq_gather_subdesc { /* SQ immediate subdescriptor */ struct sq_imm_subdesc { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t subdesc_type:4; /* W0 */ uint64_t rsvd0:46; uint64_t len:14; @@ -958,7 +956,7 @@ struct sq_imm_subdesc { }; struct sq_mem_subdesc { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t subdesc_type:4; /* W0 */ uint64_t mem_alg:4; uint64_t mem_dsz:2; @@ -982,7 +980,7 @@ struct sq_mem_subdesc { }; struct sq_hdr_subdesc { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t subdesc_type:4; uint64_t tso:1; uint64_t post_cqe:1; /* Post CQE on no error also */ @@ -1045,7 +1043,7 @@ NICVF_STATIC_ASSERT(sizeof(union sq_entry_t) == 16); /* Queue config register formats */ struct rq_cfg { union { struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t reserved_2_63:62; uint64_t ena:1; uint64_t reserved_0:1; @@ -1059,7 +1057,7 @@ struct rq_cfg { union { struct { }; }; struct cq_cfg { union { struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t reserved_43_63:21; uint64_t ena:1; uint64_t reset:1; @@ -1085,7 +1083,7 @@ struct cq_cfg { union { struct { }; }; struct sq_cfg { union { struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t reserved_20_63:44; uint64_t ena:1; uint64_t reserved_18_18:1; @@ -1111,7 +1109,7 @@ struct sq_cfg { union { struct { }; }; struct rbdr_cfg { union { struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t reserved_45_63:19; uint64_t ena:1; uint64_t reset:1; @@ -1139,7 +1137,7 @@ struct rbdr_cfg { union { struct { }; }; struct pf_qs_cfg { union { struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t reserved_32_63:32; uint64_t ena:1; uint64_t reserved_27_30:4; @@ -1169,7 +1167,7 @@ struct pf_qs_cfg { union { struct { }; }; struct pf_rq_cfg { union { struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t reserved1:1; uint64_t reserved0:34; uint64_t strip_pre_l2:1; @@ -1197,7 +1195,7 @@ struct pf_rq_cfg { union { struct { }; }; struct pf_rq_drop_cfg { union { struct { -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN uint64_t rbdr_red:1; uint64_t cq_red:1; uint64_t reserved3:14; diff --git a/drivers/net/thunderx/base/nicvf_mbox.c b/drivers/net/thunderx/base/nicvf_mbox.c index 3b7b8a5..4082e27 100644 --- a/drivers/net/thunderx/base/nicvf_mbox.c +++ b/drivers/net/thunderx/base/nicvf_mbox.c @@ -331,7 +331,7 @@ nicvf_mbox_qset_config(struct nicvf *nic, struct pf_qs_cfg *qs_cfg) { struct nic_mbx mbx = { .msg = { 0 } }; -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if NICVF_BYTE_ORDER == NICVF_BIG_ENDIAN qs_cfg->be = 1; #endif /* Send a mailbox msg to PF to config Qset */ diff --git a/drivers/net/thunderx/base/nicvf_plat.h b/drivers/net/thunderx/base/nicvf_plat.h index 3754e1b..36da120 100644 --- a/drivers/net/thunderx/base/nicvf_plat.h +++ b/drivers/net/thunderx/base/nicvf_plat.h @@ -65,6 +65,10 @@ #define nicvf_cpu_to_be_64(x) rte_cpu_to_be_64(x) #define nicvf_be_to_cpu_64(x) rte_be_to_cpu_64(x) +#define NICVF_BYTE_ORDER RTE_BYTE_ORDER +#define NICVF_BIG_ENDIAN RTE_BIG_ENDIAN +#define NICVF_LITTLE_ENDIAN RTE_LITTLE_ENDIAN + /* Constants */ #include #define NICVF_MAC_ADDR_SIZE ETHER_ADDR_LEN -- 1.9.0