[dpdk-stable] patch 'mbuf: fix VXLAN port in comment' has been queued to LTS release 16.11.3

[dpdk-stable] patch 'mbuf: fix VXLAN port in comment' has been queued to LTS release 16.11.3

[Yuanhan Liu]

Hi,

FYI, your patch has been queued to LTS release 16.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/27/17. So please
shout if anyone has objections.

Thanks.

	--yliu

---
>From f28a14808491919917f4cf258b5fd20eca0cd4d3 Mon Sep 17 00:00:00 2001
From: Cian Ferriter <cian.ferriter@intel.com>
Date: Fri, 7 Jul 2017 15:17:40 +0100
Subject: [PATCH] mbuf: fix VXLAN port in comment

[ upstream commit 838d6b775bfab436859764ea734cddaf95c7b5fd ]

IANA assigns a destination port of 4789 for the VXLAN in the Service
Name and Transport Protocol Port Number Registry. This is mentioned in
RFC 7348.

Fixes: f295a00a2b44 ("mbuf: add definitions of unified packet types")

Signed-off-by: Cian Ferriter <cian.ferriter@intel.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
---
 lib/librte_mbuf/rte_mbuf_ptype.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/librte_mbuf/rte_mbuf_ptype.h b/lib/librte_mbuf/rte_mbuf_ptype.h
index a3269c4..acd70bb 100644
--- a/lib/librte_mbuf/rte_mbuf_ptype.h
+++ b/lib/librte_mbuf/rte_mbuf_ptype.h
@@ -341,11 +341,11 @@ extern "C" {
  * Packet format:
  * <'ether type'=0x0800
  * | 'version'=4, 'protocol'=17
- * | 'destination port'=4798>
+ * | 'destination port'=4789>
  * or,
  * <'ether type'=0x86DD
  * | 'version'=6, 'next header'=17
- * | 'destination port'=4798>
+ * | 'destination port'=4789>
  */
 #define RTE_PTYPE_TUNNEL_VXLAN              0x00003000
 /**
-- 
2.7.4

[dpdk-stable] patch 'net/e1000: fix LSC interrupt' has been queued to LTS release 16.11.3

[Yuanhan Liu]

Hi,

FYI, your patch has been queued to LTS release 16.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/27/17. So please
shout if anyone has objections.

Thanks.

	--yliu

---
>From 379145b8b31c122cbf8507e111f57f897315ff95 Mon Sep 17 00:00:00 2001
From: Jingjing Wu <jingjing.wu@intel.com>
Date: Thu, 13 Jul 2017 17:43:23 +0800
Subject: [PATCH] net/e1000: fix LSC interrupt

[ upstream commit 5ed76cd749ae90206e3e58444c76faae6aa7deae ]

If LSC flag is changed to off at last device start, the
enable flag is not cleared in HW.
This patch fixes it.

Fixes: c3cd3de0ab50 ("igb: enable Rx queue interrupts for PF")

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
---
 drivers/net/e1000/igb_ethdev.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index 0a94ecc..9cf619f 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -129,7 +129,7 @@ static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 				struct rte_eth_fc_conf *fc_conf);
 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 				struct rte_eth_fc_conf *fc_conf);
-static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
+static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
@@ -1381,7 +1381,9 @@ eth_igb_start(struct rte_eth_dev *dev)
 	if (rte_intr_allow_others(intr_handle)) {
 		/* check if lsc interrupt is enabled */
 		if (dev->data->dev_conf.intr_conf.lsc != 0)
-			eth_igb_lsc_interrupt_setup(dev);
+			eth_igb_lsc_interrupt_setup(dev, TRUE);
+		else
+			eth_igb_lsc_interrupt_setup(dev, FALSE);
 	} else {
 		rte_intr_callback_unregister(intr_handle,
 					     eth_igb_interrupt_handler,
@@ -2543,18 +2545,23 @@ eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
  *
  * @param dev
  *  Pointer to struct rte_eth_dev.
+ * @param on
+ *  Enable or Disable
  *
  * @return
  *  - On success, zero.
  *  - On failure, a negative value.
  */
 static int
-eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
+eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
 {
 	struct e1000_interrupt *intr =
 		E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 
-	intr->mask |= E1000_ICR_LSC;
+	if (on)
+		intr->mask |= E1000_ICR_LSC;
+	else
+		intr->mask &= ~E1000_ICR_LSC;
 
 	return 0;
 }
-- 
2.7.4

[dpdk-stable] patch 'net/i40e: fix ethertype filter for new FW' has been queued to LTS release 16.11.3

[Yuanhan Liu]

Hi,

FYI, your patch has been queued to LTS release 16.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/27/17. So please
shout if anyone has objections.

Thanks.

	--yliu

---
>From 83eb9e99af3325e2f05e357a828b9ce5962f5c49 Mon Sep 17 00:00:00 2001
From: Beilei Xing <beilei.xing@intel.com>
Date: Tue, 18 Jul 2017 11:07:07 +0800
Subject: [PATCH] net/i40e: fix ethertype filter for new FW

[ upstream commit 77370db964f7d8a58f5914b1b805e6b093107d59 ]

Previously SW workaround for GL_SWR_PRI_JOIN_MAP is added for X710
performance. As new FW version 6.0 supports ADQ,
value for GL_SWR_PRI_JOIN_MAP should be changed, otherwise
ehtertype filter will be impacted.

Fixes: 973273c7a4b7 ("i40e: workaround for X710 performance")

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 4a1f4c8..f65ddc7 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -8343,8 +8343,9 @@ i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
  */
 
 /* For both X710 and XL710 */
-#define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
-#define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
+#define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1	0x10000200
+#define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2	0x20000200
+#define I40E_GL_SWR_PRI_JOIN_MAP_0		0x26CE00
 
 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
@@ -8396,8 +8397,12 @@ i40e_configure_registers(struct i40e_hw *hw)
 				reg_table[i].val =
 					I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
 			else /* For X710/XL710/XXV710 */
-				reg_table[i].val =
-					I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
+				if (hw->aq.fw_maj_ver < 6)
+					reg_table[i].val =
+					     I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
+				else
+					reg_table[i].val =
+					     I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
 		}
 
 		if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
-- 
2.7.4

[dpdk-stable] patch 'net/ixgbe: fix Rx/Tx queue interrupt for x550 devices' has been queued to LTS release 16.11.3

[Yuanhan Liu]

Hi,

FYI, your patch has been queued to LTS release 16.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/27/17. So please
shout if anyone has objections.

Thanks.

	--yliu

---
>From a7aa35a86c02e37aa0dcbe2b608b1a58ab9a5886 Mon Sep 17 00:00:00 2001
From: Qiming Yang <qiming.yang@intel.com>
Date: Tue, 18 Jul 2017 10:28:34 +0800
Subject: [PATCH] net/ixgbe: fix Rx/Tx queue interrupt for x550 devices

[ upstream commit 9f9d2653f19673c9c5b4d2cbf3592a7256f4771d ]

x550 devices don't map interrupt vector before enabling Rx/Tx queue
interrupt.
Because of this interrupt mode is not working for x550 devices.

Fixes: d2e72774e58c ("ixgbe/base: support X550")

Signed-off-by: Qiming Yang <qiming.yang@intel.com>
Acked-by: Wei Dai <wei.dai@intel.com>
---
 drivers/net/ixgbe/ixgbe_ethdev.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c
index d6686f6..958537f 100644
--- a/drivers/net/ixgbe/ixgbe_ethdev.c
+++ b/drivers/net/ixgbe/ixgbe_ethdev.c
@@ -5197,7 +5197,8 @@ ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 		tmp |= (msix_vector << (8 * (queue & 0x3)));
 		IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
 	} else if ((hw->mac.type == ixgbe_mac_82599EB) ||
-			(hw->mac.type == ixgbe_mac_X540)) {
+			(hw->mac.type == ixgbe_mac_X540) ||
+			(hw->mac.type == ixgbe_mac_X550)) {
 		if (direction == -1) {
 			/* other causes */
 			idx = ((queue & 1) * 8);
@@ -5303,6 +5304,7 @@ ixgbe_configure_msix(struct rte_eth_dev *dev)
 		break;
 	case ixgbe_mac_82599EB:
 	case ixgbe_mac_X540:
+	case ixgbe_mac_X550:
 		ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
 		break;
 	default:
-- 
2.7.4

[dpdk-stable] patch 'crypto/qat: fix NULL authentication hang' has been queued to LTS release 16.11.3

[Yuanhan Liu]

Hi,

FYI, your patch has been queued to LTS release 16.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/27/17. So please
shout if anyone has objections.

Thanks.

	--yliu

---
>From 6ec178f32e12ec95885936593edc7eaa5abe05eb Mon Sep 17 00:00:00 2001
From: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Date: Fri, 21 Apr 2017 09:11:30 +0100
Subject: [PATCH] crypto/qat: fix NULL authentication hang

[ upstream commit 426dc9e3018dcdb0db9b2c58405d9ee5f28b0b00 ]

To avoid a possible HW problem when dealing with
NULL authentication case, the state sizes
in the request descriptor are set.

Fixes: db0e952a5c01 ("crypto/qat: add NULL capability")

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
---
 drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 8900668..1c4b184 100644
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -99,6 +99,9 @@ static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)
 	case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_KASUMI_F9_STATE1_SZ,
 						QAT_HW_DEFAULT_ALIGNMENT);
+	case ICP_QAT_HW_AUTH_ALGO_NULL:
+		return QAT_HW_ROUND_UP(ICP_QAT_HW_NULL_STATE1_SZ,
+						QAT_HW_DEFAULT_ALIGNMENT);
 	case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
 		/* return maximum state1 size in this case */
 		return QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,
@@ -761,6 +764,9 @@ int qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc,
 		state2_size = ICP_QAT_HW_MD5_STATE2_SZ;
 		break;
 	case ICP_QAT_HW_AUTH_ALGO_NULL:
+		state1_size = qat_hash_get_state1_size(
+				ICP_QAT_HW_AUTH_ALGO_NULL);
+		state2_size = ICP_QAT_HW_NULL_STATE2_SZ;
 		break;
 	case ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:
 		state1_size = qat_hash_get_state1_size(
-- 
2.7.4

[dpdk-stable] patch 'examples/qos_sched: fix build for less lcores' has been queued to LTS release 16.11.3

[Yuanhan Liu]

Hi,

FYI, your patch has been queued to LTS release 16.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/27/17. So please
shout if anyone has objections.

Thanks.

	--yliu

---
>From 37d6029ba728edffd7ff05b9c0d2a5fad4219241 Mon Sep 17 00:00:00 2001
From: Hemant Agrawal <hemant.agrawal@nxp.com>
Date: Wed, 19 Jul 2017 13:43:10 +0530
Subject: [PATCH] examples/qos_sched: fix build for less lcores

[ upstream commit e481ebfd622c23a1d854cb4655a3534d68d322af ]

APP_MAX_LCORES is hardcoded as 64.
This will cause build err when RTE_MAX_LCORE is less then 64.

"args.c:127:22: error: iteration 8 invokes undefined behavior
	[-Werror=aggressive-loop-optimizations]
   if (cfg->lcore_role[i] == ROLE_RTE)
       ~~~~~~~~~~~~~~~^~~
args.c:126:2: note: within this loop
  for (i = 0; i < APP_MAX_LCORE; i++) {"

Fixes: d52b5e735aa3 ("examples/qos_sched: fix lcore limit")

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
 examples/qos_sched/main.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h
index c7490c6..8d02e1a 100644
--- a/examples/qos_sched/main.h
+++ b/examples/qos_sched/main.h
@@ -69,8 +69,13 @@ extern "C" {
 #define BURST_TX_DRAIN_US 100
 
 #ifndef APP_MAX_LCORE
+#if (RTE_MAX_LCORE > 64)
 #define APP_MAX_LCORE 64
+#else
+#define APP_MAX_LCORE RTE_MAX_LCORE
+#endif
 #endif
+
 #define MAX_DATA_STREAMS (APP_MAX_LCORE/2)
 #define MAX_SCHED_SUBPORTS		8
 #define MAX_SCHED_PIPES		4096
-- 
2.7.4

[dpdk-stable] patch 'examples/l2fwd-crypto: fix padding' has been queued to LTS release 16.11.3

[Yuanhan Liu]

Hi,

FYI, your patch has been queued to LTS release 16.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/27/17. So please
shout if anyone has objections.

Thanks.

	--yliu

---
>From db9af4dc38c3bced06ca4cb7a2fa8550071a2a79 Mon Sep 17 00:00:00 2001
From: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Date: Thu, 9 Feb 2017 12:27:45 +0000
Subject: [PATCH] examples/l2fwd-crypto: fix padding

[ backported from upstream commit 5839fd20e7323850f3a411d9b5642d914fa2d3f0 ]

L2fwd-crypto app was padding an incoming buffer,
to be aligned with the algorithm block size, in all cases.
This was not the right approach, as padding is only necessary
when using block cipher algorithms, such as AES-CBC.
In case of using a stream cipher algorithm, such as SNOW3G UEA2,
there is no need to include padding and increase the buffer size.

Fixes: 387259bd6c67 ("examples/l2fwd-crypto: add sample application")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
---
 examples/l2fwd-crypto/main.c | 35 ++++++++++++++++++++++++++---------
 1 file changed, 26 insertions(+), 9 deletions(-)

diff --git a/examples/l2fwd-crypto/main.c b/examples/l2fwd-crypto/main.c
index 91d2c41..b40c49c 100644
--- a/examples/l2fwd-crypto/main.c
+++ b/examples/l2fwd-crypto/main.c
@@ -432,7 +432,8 @@ l2fwd_simple_crypto_enqueue(struct rte_mbuf *m,
 	struct ether_hdr *eth_hdr;
 	struct ipv4_hdr *ip_hdr;
 
-	unsigned ipdata_offset, pad_len, data_len;
+	uint32_t ipdata_offset, data_len;
+	uint32_t pad_len = 0;
 	char *padding;
 
 	eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);
@@ -455,16 +456,32 @@ l2fwd_simple_crypto_enqueue(struct rte_mbuf *m,
 	if (cparams->do_hash && cparams->hash_verify)
 		data_len -= cparams->digest_length;
 
-	pad_len = data_len % cparams->block_size ? cparams->block_size -
-			(data_len % cparams->block_size) : 0;
+	if (cparams->do_cipher) {
+		/*
+		 * Following algorithms are block cipher algorithms,
+		 * and might need padding
+		 */
+		switch (cparams->cipher_algo) {
+		case RTE_CRYPTO_CIPHER_AES_CBC:
+		case RTE_CRYPTO_CIPHER_AES_ECB:
+		case RTE_CRYPTO_CIPHER_3DES_CBC:
+		case RTE_CRYPTO_CIPHER_3DES_ECB:
+			if (data_len % cparams->block_size)
+				pad_len = cparams->block_size -
+					(data_len % cparams->block_size);
+			break;
+		default:
+			pad_len = 0;
+		}
 
-	if (pad_len) {
-		padding = rte_pktmbuf_append(m, pad_len);
-		if (unlikely(!padding))
-			return -1;
+		if (pad_len) {
+			padding = rte_pktmbuf_append(m, pad_len);
+			if (unlikely(!padding))
+				return -1;
 
-		data_len += pad_len;
-		memset(padding, 0, pad_len);
+			data_len += pad_len;
+			memset(padding, 0, pad_len);
+		}
 	}
 
 	/* Set crypto operation data parameters */
-- 
2.7.4