From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by dpdk.org (Postfix) with ESMTP id E64AC1B1BE for ; Wed, 24 Jan 2018 16:41:50 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 9942E226D4; Wed, 24 Jan 2018 10:41:50 -0500 (EST) Received: from frontend1 ([10.202.2.160]) by compute1.internal (MEProxy); Wed, 24 Jan 2018 10:41:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fridaylinux.org; h=cc:date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=OGNWgcMpqkm9wmSOF 9O12MzFS6azkI8uq9iN8+NQW9A=; b=nX6s4m7ZtyQNL8lyWxm3PD70IgibItLmz 2h6PZWhhRYVACWCUEF8r4Rb1lwZCjULxNYcFzqfYdTIOrwYONMf6+2XlG5LGSm// VGUPixFI909c6GCDSGEvrxRTcrLr2biryoCSSouR7v/yLB4fMKH38mbJLu+vLH8c ep6z2lduNhEGw5Tvsel+nQ4p749zLAsT/nZ5hKG/9KbzrBvNeq0K41tEK/5sgWV3 uHO2XjOI9yPDloWtsqc1+uSjz8+th+7GgTBlKs4JLp52ZrTtDIRoHZrcdIq9LLvM 3wkUaoUVT42hcEJfw5dDf230gUexMiImTMUQ0Lfdac+5EFEzQQAQA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=OGNWgcMpqkm9wmSOF9O12MzFS6azkI8uq9iN8+NQW9A=; b=qZEWi51V Wz1iq3rKQ6uXTZ7Kshv2ZJ9BeSHI+HiZg1SOGkz0sCGQ1W0OUrXZTHIQhWhOsvZf CrNuLf8EH72FOk6Hbi7PQ56n5M+jj89OuyCnAntIjbpwFMDddJPsekJXHj16Bht2 o2rXwFxbz4zzBEU1Wxpm12Xh80IaemJ7nZzh6QLcx9NnBhPj9RYJOffAZ4jiRbAf qeTiDDOjFXgjOS7qm+LHOhtQF3b4+cPrZKI8ODRWDTSCBXoGD+NXReZU0NVZUDFY sYTgFi7g9I4sMpJGUTvUG+2NHwhQOp5s5b3GwmkbcrhYwNMyISaRTNVZomEOGF9k 4IAmCIVllrUUtA== X-ME-Sender: Received: from localhost.localdomain (unknown [115.150.27.206]) by mail.messagingengine.com (Postfix) with ESMTPA id 7B0F57E1BE; Wed, 24 Jan 2018 10:41:48 -0500 (EST) From: Yuanhan Liu To: Maxime Coquelin Cc: Chas Williams , dpdk stable Date: Wed, 24 Jan 2018 23:33:21 +0800 Message-Id: <1516808026-25523-133-git-send-email-yliu@fridaylinux.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1516808026-25523-1-git-send-email-yliu@fridaylinux.org> References: <1516808026-25523-1-git-send-email-yliu@fridaylinux.org> Subject: [dpdk-stable] patch 'bus/pci: forbid IOVA mode if IOMMU address width too small' has been queued to LTS release 17.11.1 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Jan 2018 15:41:51 -0000 Hi, FYI, your patch has been queued to LTS release 17.11.1 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 01/26/18. So please shout if anyone has objections. Thanks. --yliu --- >>From 3a88f146b4e8fff0b643dfd68f5d97f2c3217a3d Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Fri, 12 Jan 2018 11:22:20 +0100 Subject: [PATCH] bus/pci: forbid IOVA mode if IOMMU address width too small [ upstream commit 54a328f552ff2e0098c3f96f9e32302675f2bcf4 ] Intel VT-d supports different address widths for the IOVAs, from 39 bits to 56 bits. While recent processors support at least 48 bits, VT-d emulation currently only supports 39 bits. It makes DMA mapping to fail in this case when using VA as IOVA mode, as user-space virtual addresses uses up to 47 bits (see kernel's Documentation/x86/x86_64/mm.txt). This patch parses VT-d CAP register value available in sysfs, and forbid VA as IOVA mode if the GAW is 39 bits or unknown. Fixes: f37dfab21c98 ("drivers/net: enable IOVA mode for Intel PMDs") Signed-off-by: Maxime Coquelin Tested-by: Chas Williams --- drivers/bus/pci/linux/pci.c | 90 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 81 insertions(+), 9 deletions(-) diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c index ec31216..74deef3 100644 --- a/drivers/bus/pci/linux/pci.c +++ b/drivers/bus/pci/linux/pci.c @@ -576,6 +576,82 @@ pci_one_device_has_iova_va(void) return 0; } +#if defined(RTE_ARCH_X86) +static bool +pci_one_device_iommu_support_va(struct rte_pci_device *dev) +{ +#define VTD_CAP_MGAW_SHIFT 16 +#define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT) +#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */ + struct rte_pci_addr *addr = &dev->addr; + char filename[PATH_MAX]; + FILE *fp; + uint64_t mgaw, vtd_cap_reg = 0; + + snprintf(filename, sizeof(filename), + "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap", + rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid, + addr->function); + if (access(filename, F_OK) == -1) { + /* We don't have an Intel IOMMU, assume VA supported*/ + return true; + } + + /* We have an intel IOMMU */ + fp = fopen(filename, "r"); + if (fp == NULL) { + RTE_LOG(ERR, EAL, "%s(): can't open %s\n", __func__, filename); + return false; + } + + if (fscanf(fp, "%" PRIx64, &vtd_cap_reg) != 1) { + RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename); + fclose(fp); + return false; + } + + fclose(fp); + + mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1; + if (mgaw < X86_VA_WIDTH) + return false; + + return true; +} +#elif defined(RTE_ARCH_PPC_64) +static bool +pci_one_device_iommu_support_va(__rte_unused struct rte_pci_device *dev) +{ + return false; +} +#else +static bool +pci_one_device_iommu_support_va(__rte_unused struct rte_pci_device *dev) +{ + return true; +} +#endif + +/* + * All devices IOMMUs support VA as IOVA + */ +static bool +pci_devices_iommu_support_va(void) +{ + struct rte_pci_device *dev = NULL; + struct rte_pci_driver *drv = NULL; + + FOREACH_DRIVER_ON_PCIBUS(drv) { + FOREACH_DEVICE_ON_PCIBUS(dev) { + if (!rte_pci_match(drv, dev)) + continue; + if (!pci_one_device_iommu_support_va(dev)) + return false; + } + } + return true; +} + /* * Get iommu class of PCI devices on the bus. */ @@ -586,12 +662,7 @@ rte_pci_get_iommu_class(void) bool is_vfio_noiommu_enabled = true; bool has_iova_va; bool is_bound_uio; - bool spapr_iommu = -#if defined(RTE_ARCH_PPC_64) - true; -#else - false; -#endif + bool iommu_no_va; is_bound = pci_one_device_is_bound(); if (!is_bound) @@ -599,13 +670,14 @@ rte_pci_get_iommu_class(void) has_iova_va = pci_one_device_has_iova_va(); is_bound_uio = pci_one_device_bound_uio(); + iommu_no_va = !pci_devices_iommu_support_va(); #ifdef VFIO_PRESENT is_vfio_noiommu_enabled = rte_vfio_noiommu_is_enabled() == true ? true : false; #endif if (has_iova_va && !is_bound_uio && !is_vfio_noiommu_enabled && - !spapr_iommu) + !iommu_no_va) return RTE_IOVA_VA; if (has_iova_va) { @@ -614,8 +686,8 @@ rte_pci_get_iommu_class(void) RTE_LOG(WARNING, EAL, "vfio-noiommu mode configured\n"); if (is_bound_uio) RTE_LOG(WARNING, EAL, "few device bound to UIO\n"); - if (spapr_iommu) - RTE_LOG(WARNING, EAL, "sPAPR IOMMU does not support IOVA as VA\n"); + if (iommu_no_va) + RTE_LOG(WARNING, EAL, "IOMMU does not support IOVA as VA\n"); } return RTE_IOVA_PA; -- 2.7.4