From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by dpdk.org (Postfix) with ESMTP id 72EA54D3A for ; Thu, 1 Feb 2018 10:49:35 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 2CEAD208B8; Thu, 1 Feb 2018 04:49:35 -0500 (EST) Received: from frontend2 ([10.202.2.161]) by compute1.internal (MEProxy); Thu, 01 Feb 2018 04:49:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fridaylinux.org; h=cc:date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=NvqLYsumtJkeffDlk 2TcBoIZn8hzx47iUqIEtw6CkFY=; b=PEl2aG+VHk6RJgBjKnaATctIUaOafPn/G C6nNn7L4XO3U6YhOfbrHR6b+6gxQm/cnDj/Pzx8YUYUQ6pVYpwgWwR7UsdDPZblm chyI7J0+qrS2eledLqUFouVnzlk0A4gmhgbWSFcokO0RT7YnGytHpZfxlX1EK5JY vPZUH7yh7PibE4lIY3I6DCUotR3CgFPb3dxEU7XzIPcbrOHHUBa79HkMb0UyynSx Ixk3mtT6b9TdrDyENt0iheoBC10vpS0z9YbpbgLkPzO2SAHRnl+ux0XktcKVpTRH 8O9pAnRjuG4bl5nzNuBlIRmplq0fZUGp3/py1HykUzRam5aTXLm9A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=NvqLYsumtJkeffDlk2TcBoIZn8hzx47iUqIEtw6CkFY=; b=Y2lorU1D AkxoNnIKletiOF5EqOFqHr5hwkYo3x29rBEiFOvpaa3yIdpfLe0CyFjq2vAydOFo 545baAnWHtmD3xt1O3rfbVqNOZkQrnaIO73HYIrxkb2j/vDT/JiTEJeFBMX4tP7K YUPzUeXh7RyrA5/N6wlNwJU3oLPz7AR4NGZHqPNNhc5OscZmSbl83dmn6D9uPJ9R BR4XOJC9FrEws7f6AOW3Q/aTN7I0exZcuxKmMys2CAqRWioIKkxuvAoQsLUe2FjX nMjAjL4VwjeQXd68jwD0MlHPDRmBSpoS9kBSQOQm+Z2mVCp4RSIMGat/FPtm0ZwZ a/fNqz4QOkXerA== X-ME-Sender: Received: from yliu-mob.mtl.com (unknown [115.150.27.200]) by mail.messagingengine.com (Postfix) with ESMTPA id E0C3024610; Thu, 1 Feb 2018 04:49:33 -0500 (EST) From: Yuanhan Liu To: Gowrishankar Muthukrishnan Cc: dpdk stable Date: Thu, 1 Feb 2018 17:47:49 +0800 Message-Id: <1517478479-12417-35-git-send-email-yliu@fridaylinux.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517478479-12417-1-git-send-email-yliu@fridaylinux.org> References: <1517478479-12417-1-git-send-email-yliu@fridaylinux.org> Subject: [dpdk-stable] patch 'eal/ppc: remove the braces in memory barrier macros' has been queued to LTS release 17.11.1 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 09:49:35 -0000 Hi, FYI, your patch has been queued to LTS release 17.11.1 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 02/03/18. So please shout if anyone has objections. Thanks. --yliu --- >>From 5630769259bf69955fa3ab45da026798960bb047 Mon Sep 17 00:00:00 2001 From: Gowrishankar Muthukrishnan Date: Tue, 30 Jan 2018 16:23:18 +0530 Subject: [PATCH] eal/ppc: remove the braces in memory barrier macros [ upstream commit 257515a50057fa97605cc13e5b3b9cc9f964c299 ] Calling rte_smp_{w/r}mb macro expands into a compound block, which would break compiling a else clause following it, if that calling place has been terminated already with ";", as in below code. This patch adds { } around this macro to allow compiling else too. Fixes: d23a6bd04d ("eal/ppc: fix memory barrier for IBM POWER") Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power") Signed-off-by: Gowrishankar Muthukrishnan --- lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h index 150810c..6993dd2 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h @@ -64,9 +64,9 @@ extern "C" { * occur before the STORE operations generated after. */ #ifdef RTE_ARCH_64 -#define rte_wmb() {asm volatile("lwsync" : : : "memory"); } +#define rte_wmb() asm volatile("lwsync" : : : "memory") #else -#define rte_wmb() {asm volatile("sync" : : : "memory"); } +#define rte_wmb() asm volatile("sync" : : : "memory") #endif /** @@ -76,9 +76,9 @@ extern "C" { * occur before the LOAD operations generated after. */ #ifdef RTE_ARCH_64 -#define rte_rmb() {asm volatile("lwsync" : : : "memory"); } +#define rte_rmb() asm volatile("lwsync" : : : "memory") #else -#define rte_rmb() {asm volatile("sync" : : : "memory"); } +#define rte_rmb() asm volatile("sync" : : : "memory") #endif #define rte_smp_mb() rte_mb() -- 2.7.4