From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id DC2C01B89C for ; Fri, 9 Feb 2018 08:41:06 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Feb 2018 23:41:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,482,1511856000"; d="scan'208";a="202805056" Received: from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52]) by fmsmga006.fm.intel.com with ESMTP; 08 Feb 2018 23:41:03 -0800 From: Beilei Xing To: stable@dpdk.org Date: Fri, 9 Feb 2018 15:41:36 +0800 Message-Id: <1518162100-106136-2-git-send-email-beilei.xing@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1518162100-106136-1-git-send-email-beilei.xing@intel.com> References: <1518162100-106136-1-git-send-email-beilei.xing@intel.com> Subject: [dpdk-stable] [BACKPORT 1/5] net/i40e: warn when writing global registers X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Feb 2018 07:41:07 -0000 [ upstream commit 399c635c390121e8c7a7d6df72ef97a75ad8ee44 ] Add warnings when writing global registers. Signed-off-by: Beilei Xing --- doc/guides/nics/i40e.rst | 12 ++++++++++++ drivers/net/i40e/i40e_ethdev.c | 25 ++++++++++++++++++++++++ drivers/net/i40e/i40e_ethdev.h | 43 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+) diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst index cd46874..efbc431 100644 --- a/doc/guides/nics/i40e.rst +++ b/doc/guides/nics/i40e.rst @@ -483,6 +483,18 @@ Vlan strip of VF The VF vlan strip function is only supported in the i40e kernel driver >= 2.1.26. +Global configuration warning +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +I40E PMD will set some global registers to enable some function or set some +configure. Then when using different ports of the same NIC with Linux kernel +and DPDK, the port with Linux kernel will be impacted by the port with DPDK. +For example, register I40E_GL_SWT_L2TAGCTRL is used to control L2 tag, i40e +PMD uses I40E_GL_SWT_L2TAGCTRL to set vlan TPID. If setting TPID in port A +with DPDK, then the configuration will also impact port B in the NIC with +kernel driver, which don't want to use the TPID. +So PMD reports warning to clarify what is changed by writing global register. + High Performance of Small Packets on 40G NIC -------------------------------------------- diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 5f2c504..799cb16 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -710,6 +710,7 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0); I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3); I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6); + i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD); /* * Initialize registers for parsing packet type of QinQ @@ -719,6 +720,7 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) */ I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029); I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420); + i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER); } #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808 @@ -1173,6 +1175,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) 0x00000028, NULL); if (ret) PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret); + i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER); /* Need the special FW version to support floating VEB */ config_floating_veb(dev); @@ -3267,6 +3270,7 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev, /* If NVM API < 1.7, keep the register setting */ ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type, tpid, qinq); + i40e_global_cfg_warning(I40E_WARNING_TPID); return ret; } @@ -3509,6 +3513,7 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) I40E_WRITE_REG(hw, I40E_GLRPB_GLW, pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] << I40E_KILOSHIFT); + i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL); I40E_WRITE_FLUSH(hw); @@ -7183,6 +7188,8 @@ i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf) status = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); + if (!status) + i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); return status; } @@ -7237,6 +7244,8 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf) status = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); + if (!status) + i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); return status; } @@ -7304,6 +7313,8 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf) status = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); + if (!status) + i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); return status; } @@ -7356,6 +7367,8 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf) status = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); + if (!status) + i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); return status; } @@ -7905,6 +7918,7 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len) reg, NULL); if (ret != 0) return ret; + i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN); } else { ret = 0; } @@ -8164,6 +8178,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw, I40E_GLQF_HSYM(j), reg); } + i40e_global_cfg_warning(I40E_WARNING_HSYM); } } @@ -8189,6 +8204,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw, goto out; i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg); + i40e_global_cfg_warning(I40E_WARNING_QF_CTL); out: I40E_WRITE_FLUSH(hw); @@ -8833,6 +8849,10 @@ i40e_filter_input_set_init(struct i40e_pf *pf) pf->hash_input_set[pctype] = input_set; pf->fdir.input_set[pctype] = input_set; } + + i40e_global_cfg_warning(I40E_WARNING_HASH_INSET); + i40e_global_cfg_warning(I40E_WARNING_FD_MSK); + i40e_global_cfg_warning(I40E_WARNING_HASH_MSK); } int @@ -8893,6 +8913,7 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw, i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype), (uint32_t)((inset_reg >> I40E_32_BIT_WIDTH) & UINT32_MAX)); + i40e_global_cfg_warning(I40E_WARNING_HASH_INSET); for (i = 0; i < num; i++) i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), @@ -8901,6 +8922,7 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw, for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype), 0); + i40e_global_cfg_warning(I40E_WARNING_HASH_MSK); I40E_WRITE_FLUSH(hw); pf->hash_input_set[pctype] = input_set; @@ -8974,6 +8996,7 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf, for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0); + i40e_global_cfg_warning(I40E_WARNING_FD_MSK); I40E_WRITE_FLUSH(hw); pf->fdir.input_set[pctype] = input_set; @@ -11476,6 +11499,8 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf) I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED; ret = i40e_aq_replace_cloud_filters(hw, &filter_replace, &filter_replace_buf); + if (!ret) + i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER); return ret; } diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index cd67453..f24555d 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -1084,6 +1084,22 @@ struct i40e_valid_pattern { parse_filter_t parse_filter; }; +enum I40E_WARNING_IDX { + I40E_WARNING_DIS_FLX_PLD, + I40E_WARNING_ENA_FLX_PLD, + I40E_WARNING_QINQ_PARSER, + I40E_WARNING_QINQ_CLOUD_FILTER, + I40E_WARNING_TPID, + I40E_WARNING_FLOW_CTL, + I40E_WARNING_GRE_KEY_LEN, + I40E_WARNING_QF_CTL, + I40E_WARNING_HASH_INSET, + I40E_WARNING_HSYM, + I40E_WARNING_HASH_MSK, + I40E_WARNING_FD_MSK, + I40E_WARNING_RPL_CLD_FILTER, +}; + int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); int i40e_vsi_release(struct i40e_vsi *vsi); struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, @@ -1283,6 +1299,33 @@ i40e_calc_itr_interval(int16_t interval) return interval / 2; } +static inline void +i40e_global_cfg_warning(enum I40E_WARNING_IDX idx) +{ + const char *warning; + static const char *const warning_list[] = { + [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload", + [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload", + [I40E_WARNING_QINQ_PARSER] = "support QinQ parser", + [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter", + [I40E_WARNING_TPID] = "support TPID configuration", + [I40E_WARNING_FLOW_CTL] = "configure water marker", + [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting", + [I40E_WARNING_QF_CTL] = "support hash function setting", + [I40E_WARNING_HASH_INSET] = "configure hash input set", + [I40E_WARNING_HSYM] = "set symmetric hash", + [I40E_WARNING_HASH_MSK] = "configure hash mask", + [I40E_WARNING_FD_MSK] = "configure fdir mask", + [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter", + }; + + warning = warning_list[idx]; + + RTE_LOG(WARNING, PMD, + "Global register is changed during %s\n", + warning); +} + #define I40E_VALID_FLOW(flow_type) \ ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \ -- 2.5.5