* [dpdk-stable] [PATCH 0/3] add AES-CMAC support
@ 2018-09-28 18:10 Tomasz Cel
2018-09-28 18:10 ` [dpdk-stable] [PATCH 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
` (5 more replies)
0 siblings, 6 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-09-28 18:10 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, Tomasz Cel
This patch add support, update QAT documentation and enable tests for AES-CMAC.
Tomasz Cel (3):
crypto/qat: add support AES-CMAC
test/qat: test for AES-CMAC
doc/qat: add AES-CMAC to the QAT feature list
doc/guides/cryptodevs/features/qat.ini | 25 ++--
drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++--------
drivers/crypto/qat/qat_sym_session.h | 3 +
test/test/test_cryptodev_hash_test_vectors.h | 12 +-
4 files changed, 160 insertions(+), 70 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH 1/3] crypto/qat: add support AES-CMAC
2018-09-28 18:10 [dpdk-stable] [PATCH 0/3] add AES-CMAC support Tomasz Cel
@ 2018-09-28 18:10 ` Tomasz Cel
2018-09-28 18:10 ` [dpdk-stable] [PATCH 2/3] test/qat: test for AES-CMAC Tomasz Cel
` (4 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-09-28 18:10 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, Tomasz Cel
This patch add AES-CMAC support. CMAC is a keyed hash function
that is based on a symmetric key block cipher. It is One-Key
CBC MAC improvement over XCBC-MAC. RFC 4493. NIST SP 800-38B.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++++++++----------
drivers/crypto/qat/qat_sym_session.h | 3 +
2 files changed, 139 insertions(+), 54 deletions(-)
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 1d58220..8196e23 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -498,6 +498,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
struct qat_sym_dev_private *internals = dev->data->dev_private;
uint8_t *key_data = auth_xform->key.data;
uint8_t key_length = auth_xform->key.length;
+ session->aes_cmac = 0;
switch (auth_xform->algo) {
case RTE_CRYPTO_AUTH_SHA1_HMAC:
@@ -518,6 +519,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
break;
+ case RTE_CRYPTO_AUTH_AES_CMAC:
+ session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
+ session->aes_cmac = 1;
+ break;
case RTE_CRYPTO_AUTH_AES_GMAC:
if (qat_sym_validate_aes_key(auth_xform->key.length,
&session->qat_cipher_alg) != 0) {
@@ -555,7 +560,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
case RTE_CRYPTO_AUTH_SHA224:
case RTE_CRYPTO_AUTH_SHA384:
case RTE_CRYPTO_AUTH_MD5:
- case RTE_CRYPTO_AUTH_AES_CMAC:
case RTE_CRYPTO_AUTH_AES_CBC_MAC:
QAT_LOG(ERR, "Crypto: Unsupported hash alg %u",
auth_xform->algo);
@@ -817,6 +821,8 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
return ICP_QAT_HW_SHA512_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
return ICP_QAT_HW_MD5_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
+ return ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum digest size in this case */
return ICP_QAT_HW_SHA512_STATE1_SZ;
@@ -843,6 +849,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
return SHA512_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
return 16;
+ case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
+ return ICP_QAT_HW_AES_BLK_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
return MD5_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
@@ -991,11 +999,28 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
#define HMAC_OPAD_VALUE 0x5c
#define HASH_XCBC_PRECOMP_KEY_NUM 3
+static const uint8_t AES_CMAC_SEED[ICP_QAT_HW_AES_128_KEY_SZ];
+
+static void aes_cmac_key_derive(uint8_t *base, uint8_t *derived)
+{
+ int i;
+
+ derived[0] = base[0] << 1;
+ for (i = 1; i < ICP_QAT_HW_AES_BLK_SZ ; i++) {
+ derived[i] = base[i] << 1;
+ derived[i - 1] |= base[i] >> 7;
+ }
+
+ if (base[0] & 0x80)
+ derived[ICP_QAT_HW_AES_BLK_SZ - 1] ^= QAT_AES_CMAC_CONST_RB;
+}
+
static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
const uint8_t *auth_key,
uint16_t auth_keylen,
uint8_t *p_state_buf,
- uint16_t *p_state_len)
+ uint16_t *p_state_len,
+ uint8_t aes_cmac)
{
int block_size;
uint8_t ipad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
@@ -1003,47 +1028,91 @@ static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
int i;
if (hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC) {
- static uint8_t qat_aes_xcbc_key_seed[
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- };
- uint8_t *in = NULL;
- uint8_t *out = p_state_buf;
- int x;
- AES_KEY enc_key;
+ /* CMAC */
+ if (aes_cmac) {
+ AES_KEY enc_key;
+ uint8_t *in = NULL;
+ uint8_t k0[ICP_QAT_HW_AES_128_KEY_SZ];
+ uint8_t *k1, *k2;
- in = rte_zmalloc("working mem for key",
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
- if (in == NULL) {
- QAT_LOG(ERR, "Failed to alloc memory");
- return -ENOMEM;
- }
+ auth_keylen = ICP_QAT_HW_AES_128_KEY_SZ;
+
+ in = rte_zmalloc("AES CMAC K1",
+ ICP_QAT_HW_AES_128_KEY_SZ, 16);
+
+ if (in == NULL) {
+ QAT_LOG(ERR, "Failed to alloc memory");
+ return -ENOMEM;
+ }
+
+ rte_memcpy(in, AES_CMAC_SEED,
+ ICP_QAT_HW_AES_128_KEY_SZ);
+ rte_memcpy(p_state_buf, auth_key, auth_keylen);
- rte_memcpy(in, qat_aes_xcbc_key_seed,
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
- for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
&enc_key) != 0) {
- rte_free(in -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
- memset(out -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
- 0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ rte_free(in);
return -EFAULT;
}
- AES_encrypt(in, out, &enc_key);
- in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
- out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+
+ AES_encrypt(in, k0, &enc_key);
+
+ k1 = p_state_buf + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+ k2 = k1 + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+
+ aes_cmac_key_derive(k0, k1);
+ aes_cmac_key_derive(k1, k2);
+
+ memset(k0, 0, ICP_QAT_HW_AES_128_KEY_SZ);
+ *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
+ rte_free(in);
+ return 0;
+ } else {
+ static uint8_t qat_aes_xcbc_key_seed[
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ };
+
+ uint8_t *in = NULL;
+ uint8_t *out = p_state_buf;
+ int x;
+ AES_KEY enc_key;
+
+ in = rte_zmalloc("working mem for key",
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
+ if (in == NULL) {
+ QAT_LOG(ERR, "Failed to alloc memory");
+ return -ENOMEM;
+ }
+
+ rte_memcpy(in, qat_aes_xcbc_key_seed,
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
+ if (AES_set_encrypt_key(auth_key,
+ auth_keylen << 3,
+ &enc_key) != 0) {
+ rte_free(in -
+ (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
+ memset(out -
+ (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
+ 0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ return -EFAULT;
+ }
+ AES_encrypt(in, out, &enc_key);
+ in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+ out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+ }
+ *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
+ rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
+ return 0;
}
- *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
- rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
- return 0;
+
} else if ((hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
(hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
uint8_t *in = NULL;
@@ -1417,7 +1486,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9
- || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3)
+ || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3
+ || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC
+ )
hash->auth_counter.counter = 0;
else
hash->auth_counter.counter = rte_bswap32(
@@ -1430,40 +1501,45 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
*/
switch (cdesc->qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
break;
case ICP_QAT_HW_AUTH_ALGO_SHA224:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA384:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
@@ -1471,10 +1547,16 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
break;
case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
state1_size = ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+
+ if (cdesc->aes_cmac)
+ memset(cdesc->cd_cur_ptr, 0, state1_size);
if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC,
authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size)) {
- QAT_LOG(ERR, "(XCBC)precompute failed");
+ &state2_size, cdesc->aes_cmac)) {
+ cdesc->aes_cmac ? QAT_LOG(ERR,
+ "(CMAC)precompute failed")
+ : QAT_LOG(ERR,
+ "(XCBC)precompute failed");
return -EFAULT;
}
break;
@@ -1482,9 +1564,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;
state1_size = ICP_QAT_HW_GALOIS_128_STATE1_SZ;
- if (qat_sym_do_precomputes(cdesc->qat_hash_alg,
- authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size)) {
+ if (qat_sym_do_precomputes(cdesc->qat_hash_alg, authkey,
+ authkeylen, cdesc->cd_cur_ptr + state1_size,
+ &state2_size, cdesc->aes_cmac)) {
QAT_LOG(ERR, "(GCM)precompute failed");
return -EFAULT;
}
@@ -1542,9 +1624,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
break;
case ICP_QAT_HW_AUTH_ALGO_MD5:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5,
- authkey, authkeylen, cdesc->cd_cur_ptr,
- &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(MD5)precompute failed");
return -EFAULT;
}
diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h
index e8f51e5..43e25ce 100644
--- a/drivers/crypto/qat/qat_sym_session.h
+++ b/drivers/crypto/qat/qat_sym_session.h
@@ -36,6 +36,8 @@
ICP_QAT_HW_CIPHER_KEY_CONVERT, \
ICP_QAT_HW_CIPHER_DECRYPT)
+#define QAT_AES_CMAC_CONST_RB 0x87
+
enum qat_sym_proto_flag {
QAT_CRYPTO_PROTO_FLAG_NONE = 0,
QAT_CRYPTO_PROTO_FLAG_CCM = 1,
@@ -75,6 +77,7 @@ struct qat_sym_session {
uint16_t digest_length;
rte_spinlock_t lock; /* protects this struct */
enum qat_device_gen min_qat_dev_gen;
+ uint8_t aes_cmac;
};
int
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH 2/3] test/qat: test for AES-CMAC
2018-09-28 18:10 [dpdk-stable] [PATCH 0/3] add AES-CMAC support Tomasz Cel
2018-09-28 18:10 ` [dpdk-stable] [PATCH 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
@ 2018-09-28 18:10 ` Tomasz Cel
2018-09-28 18:10 ` [dpdk-stable] [PATCH 3/3] doc/qat: add AES-CMAC to the QAT feature list Tomasz Cel
` (3 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-09-28 18:10 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, Tomasz Cel
Enable tests for AES-CMAC authentication algorithm.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
---
test/test/test_cryptodev_hash_test_vectors.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/test/test/test_cryptodev_hash_test_vectors.h b/test/test/test_cryptodev_hash_test_vectors.h
index cf86dbb..8b6349c 100644
--- a/test/test/test_cryptodev_hash_test_vectors.h
+++ b/test/test/test_cryptodev_hash_test_vectors.h
@@ -634,25 +634,29 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.test_descr = "CMAC Digest 12B",
.test_data = &cmac_test_vector_12,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest Verify 12B",
.test_data = &cmac_test_vector_12,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest 16B",
.test_data = &cmac_test_vector,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest Verify 16B",
.test_data = &cmac_test_vector,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
}
};
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH 3/3] doc/qat: add AES-CMAC to the QAT feature list
2018-09-28 18:10 [dpdk-stable] [PATCH 0/3] add AES-CMAC support Tomasz Cel
2018-09-28 18:10 ` [dpdk-stable] [PATCH 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
2018-09-28 18:10 ` [dpdk-stable] [PATCH 2/3] test/qat: test for AES-CMAC Tomasz Cel
@ 2018-09-28 18:10 ` Tomasz Cel
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Tomasz Cel
` (2 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-09-28 18:10 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, Tomasz Cel
Update the QAT documentation to show that it supports AES-CMAC.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
---
doc/guides/cryptodevs/features/qat.ini | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini
index 220291b..41baa46 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -36,18 +36,19 @@ ZUC EEA3 = Y
; Supported authentication algorithms of the 'qat' crypto driver.
;
[Auth]
-NULL = Y
-MD5 HMAC = Y
-SHA1 HMAC = Y
-SHA224 HMAC = Y
-SHA256 HMAC = Y
-SHA384 HMAC = Y
-SHA512 HMAC = Y
-AES GMAC = Y
-SNOW3G UIA2 = Y
-KASUMI F9 = Y
-AES XCBC MAC = Y
-ZUC EIA3 = Y
+NULL = Y
+MD5 HMAC = Y
+SHA1 HMAC = Y
+SHA224 HMAC = Y
+SHA256 HMAC = Y
+SHA384 HMAC = Y
+SHA512 HMAC = Y
+AES GMAC = Y
+SNOW3G UIA2 = Y
+KASUMI F9 = Y
+AES XCBC MAC = Y
+ZUC EIA3 = Y
+AES CMAC (128) = Y
;
; Supported AEAD algorithms of the 'qat' crypto driver.
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support
2018-09-28 18:10 [dpdk-stable] [PATCH 0/3] add AES-CMAC support Tomasz Cel
` (2 preceding siblings ...)
2018-09-28 18:10 ` [dpdk-stable] [PATCH 3/3] doc/qat: add AES-CMAC to the QAT feature list Tomasz Cel
@ 2018-10-04 11:22 ` Tomasz Cel
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
` (3 more replies)
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 " Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Tomasz Cel
5 siblings, 4 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-04 11:22 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, Tomasz Cel
This patch add support, update QAT documentation and enable tests for AES-CMAC.
v2:
* deleted unnecessary white signs from documentation part
Tomasz Cel (3):
crypto/qat: add support AES-CMAC
test/qat: test for AES-CMAC
doc/qat: add AES-CMAC to the QAT feature list
doc/guides/cryptodevs/features/qat.ini | 1 +
drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++--------
drivers/crypto/qat/qat_sym_session.h | 3 +
test/test/test_cryptodev_hash_test_vectors.h | 12 +-
4 files changed, 148 insertions(+), 58 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v2 1/3] crypto/qat: add support AES-CMAC
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Tomasz Cel
@ 2018-10-04 11:22 ` Tomasz Cel
2018-10-05 12:02 ` [dpdk-stable] [dpdk-dev] " Mattias Rönnblom
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 2/3] test/qat: test for AES-CMAC Tomasz Cel
` (2 subsequent siblings)
3 siblings, 1 reply; 21+ messages in thread
From: Tomasz Cel @ 2018-10-04 11:22 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, Tomasz Cel
This patch add AES-CMAC support. CMAC is a keyed hash function
that is based on a symmetric key block cipher. It is One-Key
CBC MAC improvement over XCBC-MAC. RFC 4493. NIST SP 800-38B.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++++++++----------
drivers/crypto/qat/qat_sym_session.h | 3 +
2 files changed, 139 insertions(+), 54 deletions(-)
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 1d58220..8196e23 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -498,6 +498,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
struct qat_sym_dev_private *internals = dev->data->dev_private;
uint8_t *key_data = auth_xform->key.data;
uint8_t key_length = auth_xform->key.length;
+ session->aes_cmac = 0;
switch (auth_xform->algo) {
case RTE_CRYPTO_AUTH_SHA1_HMAC:
@@ -518,6 +519,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
break;
+ case RTE_CRYPTO_AUTH_AES_CMAC:
+ session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
+ session->aes_cmac = 1;
+ break;
case RTE_CRYPTO_AUTH_AES_GMAC:
if (qat_sym_validate_aes_key(auth_xform->key.length,
&session->qat_cipher_alg) != 0) {
@@ -555,7 +560,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
case RTE_CRYPTO_AUTH_SHA224:
case RTE_CRYPTO_AUTH_SHA384:
case RTE_CRYPTO_AUTH_MD5:
- case RTE_CRYPTO_AUTH_AES_CMAC:
case RTE_CRYPTO_AUTH_AES_CBC_MAC:
QAT_LOG(ERR, "Crypto: Unsupported hash alg %u",
auth_xform->algo);
@@ -817,6 +821,8 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
return ICP_QAT_HW_SHA512_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
return ICP_QAT_HW_MD5_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
+ return ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum digest size in this case */
return ICP_QAT_HW_SHA512_STATE1_SZ;
@@ -843,6 +849,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
return SHA512_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
return 16;
+ case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
+ return ICP_QAT_HW_AES_BLK_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
return MD5_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
@@ -991,11 +999,28 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
#define HMAC_OPAD_VALUE 0x5c
#define HASH_XCBC_PRECOMP_KEY_NUM 3
+static const uint8_t AES_CMAC_SEED[ICP_QAT_HW_AES_128_KEY_SZ];
+
+static void aes_cmac_key_derive(uint8_t *base, uint8_t *derived)
+{
+ int i;
+
+ derived[0] = base[0] << 1;
+ for (i = 1; i < ICP_QAT_HW_AES_BLK_SZ ; i++) {
+ derived[i] = base[i] << 1;
+ derived[i - 1] |= base[i] >> 7;
+ }
+
+ if (base[0] & 0x80)
+ derived[ICP_QAT_HW_AES_BLK_SZ - 1] ^= QAT_AES_CMAC_CONST_RB;
+}
+
static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
const uint8_t *auth_key,
uint16_t auth_keylen,
uint8_t *p_state_buf,
- uint16_t *p_state_len)
+ uint16_t *p_state_len,
+ uint8_t aes_cmac)
{
int block_size;
uint8_t ipad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
@@ -1003,47 +1028,91 @@ static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
int i;
if (hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC) {
- static uint8_t qat_aes_xcbc_key_seed[
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- };
- uint8_t *in = NULL;
- uint8_t *out = p_state_buf;
- int x;
- AES_KEY enc_key;
+ /* CMAC */
+ if (aes_cmac) {
+ AES_KEY enc_key;
+ uint8_t *in = NULL;
+ uint8_t k0[ICP_QAT_HW_AES_128_KEY_SZ];
+ uint8_t *k1, *k2;
- in = rte_zmalloc("working mem for key",
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
- if (in == NULL) {
- QAT_LOG(ERR, "Failed to alloc memory");
- return -ENOMEM;
- }
+ auth_keylen = ICP_QAT_HW_AES_128_KEY_SZ;
+
+ in = rte_zmalloc("AES CMAC K1",
+ ICP_QAT_HW_AES_128_KEY_SZ, 16);
+
+ if (in == NULL) {
+ QAT_LOG(ERR, "Failed to alloc memory");
+ return -ENOMEM;
+ }
+
+ rte_memcpy(in, AES_CMAC_SEED,
+ ICP_QAT_HW_AES_128_KEY_SZ);
+ rte_memcpy(p_state_buf, auth_key, auth_keylen);
- rte_memcpy(in, qat_aes_xcbc_key_seed,
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
- for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
&enc_key) != 0) {
- rte_free(in -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
- memset(out -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
- 0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ rte_free(in);
return -EFAULT;
}
- AES_encrypt(in, out, &enc_key);
- in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
- out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+
+ AES_encrypt(in, k0, &enc_key);
+
+ k1 = p_state_buf + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+ k2 = k1 + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+
+ aes_cmac_key_derive(k0, k1);
+ aes_cmac_key_derive(k1, k2);
+
+ memset(k0, 0, ICP_QAT_HW_AES_128_KEY_SZ);
+ *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
+ rte_free(in);
+ return 0;
+ } else {
+ static uint8_t qat_aes_xcbc_key_seed[
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ };
+
+ uint8_t *in = NULL;
+ uint8_t *out = p_state_buf;
+ int x;
+ AES_KEY enc_key;
+
+ in = rte_zmalloc("working mem for key",
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
+ if (in == NULL) {
+ QAT_LOG(ERR, "Failed to alloc memory");
+ return -ENOMEM;
+ }
+
+ rte_memcpy(in, qat_aes_xcbc_key_seed,
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
+ if (AES_set_encrypt_key(auth_key,
+ auth_keylen << 3,
+ &enc_key) != 0) {
+ rte_free(in -
+ (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
+ memset(out -
+ (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
+ 0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ return -EFAULT;
+ }
+ AES_encrypt(in, out, &enc_key);
+ in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+ out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+ }
+ *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
+ rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
+ return 0;
}
- *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
- rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
- return 0;
+
} else if ((hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
(hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
uint8_t *in = NULL;
@@ -1417,7 +1486,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9
- || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3)
+ || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3
+ || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC
+ )
hash->auth_counter.counter = 0;
else
hash->auth_counter.counter = rte_bswap32(
@@ -1430,40 +1501,45 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
*/
switch (cdesc->qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
break;
case ICP_QAT_HW_AUTH_ALGO_SHA224:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA384:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
@@ -1471,10 +1547,16 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
break;
case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
state1_size = ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+
+ if (cdesc->aes_cmac)
+ memset(cdesc->cd_cur_ptr, 0, state1_size);
if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC,
authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size)) {
- QAT_LOG(ERR, "(XCBC)precompute failed");
+ &state2_size, cdesc->aes_cmac)) {
+ cdesc->aes_cmac ? QAT_LOG(ERR,
+ "(CMAC)precompute failed")
+ : QAT_LOG(ERR,
+ "(XCBC)precompute failed");
return -EFAULT;
}
break;
@@ -1482,9 +1564,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;
state1_size = ICP_QAT_HW_GALOIS_128_STATE1_SZ;
- if (qat_sym_do_precomputes(cdesc->qat_hash_alg,
- authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size)) {
+ if (qat_sym_do_precomputes(cdesc->qat_hash_alg, authkey,
+ authkeylen, cdesc->cd_cur_ptr + state1_size,
+ &state2_size, cdesc->aes_cmac)) {
QAT_LOG(ERR, "(GCM)precompute failed");
return -EFAULT;
}
@@ -1542,9 +1624,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
break;
case ICP_QAT_HW_AUTH_ALGO_MD5:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5,
- authkey, authkeylen, cdesc->cd_cur_ptr,
- &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(MD5)precompute failed");
return -EFAULT;
}
diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h
index e8f51e5..43e25ce 100644
--- a/drivers/crypto/qat/qat_sym_session.h
+++ b/drivers/crypto/qat/qat_sym_session.h
@@ -36,6 +36,8 @@
ICP_QAT_HW_CIPHER_KEY_CONVERT, \
ICP_QAT_HW_CIPHER_DECRYPT)
+#define QAT_AES_CMAC_CONST_RB 0x87
+
enum qat_sym_proto_flag {
QAT_CRYPTO_PROTO_FLAG_NONE = 0,
QAT_CRYPTO_PROTO_FLAG_CCM = 1,
@@ -75,6 +77,7 @@ struct qat_sym_session {
uint16_t digest_length;
rte_spinlock_t lock; /* protects this struct */
enum qat_device_gen min_qat_dev_gen;
+ uint8_t aes_cmac;
};
int
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v2 2/3] test/qat: test for AES-CMAC
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Tomasz Cel
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
@ 2018-10-04 11:22 ` Tomasz Cel
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 3/3] doc/qat: add AES-CMAC to the QAT feature list Tomasz Cel
2018-10-04 11:47 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Trahe, Fiona
3 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-04 11:22 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, Tomasz Cel
Enable tests for AES-CMAC authentication algorithm.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
---
test/test/test_cryptodev_hash_test_vectors.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/test/test/test_cryptodev_hash_test_vectors.h b/test/test/test_cryptodev_hash_test_vectors.h
index cf86dbb..8b6349c 100644
--- a/test/test/test_cryptodev_hash_test_vectors.h
+++ b/test/test/test_cryptodev_hash_test_vectors.h
@@ -634,25 +634,29 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.test_descr = "CMAC Digest 12B",
.test_data = &cmac_test_vector_12,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest Verify 12B",
.test_data = &cmac_test_vector_12,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest 16B",
.test_data = &cmac_test_vector,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest Verify 16B",
.test_data = &cmac_test_vector,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
}
};
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v2 3/3] doc/qat: add AES-CMAC to the QAT feature list
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Tomasz Cel
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 2/3] test/qat: test for AES-CMAC Tomasz Cel
@ 2018-10-04 11:22 ` Tomasz Cel
2018-10-04 11:47 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Trahe, Fiona
3 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-04 11:22 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, Tomasz Cel
Update the QAT documentation to show that it supports AES-CMAC.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
---
doc/guides/cryptodevs/features/qat.ini | 1 +
1 file changed, 1 insertion(+)
diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini
index 220291b..4f15ee0 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -48,6 +48,7 @@ SNOW3G UIA2 = Y
KASUMI F9 = Y
AES XCBC MAC = Y
ZUC EIA3 = Y
+AES CMAC (128) = Y
;
; Supported AEAD algorithms of the 'qat' crypto driver.
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Tomasz Cel
` (2 preceding siblings ...)
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 3/3] doc/qat: add AES-CMAC to the QAT feature list Tomasz Cel
@ 2018-10-04 11:47 ` Trahe, Fiona
3 siblings, 0 replies; 21+ messages in thread
From: Trahe, Fiona @ 2018-10-04 11:47 UTC (permalink / raw)
To: Cel, TomaszX, dev
Cc: stable, akhil.goyal, Kovacevic, Marko, Kusztal, ArkadiuszX, Trahe, Fiona
> -----Original Message-----
> From: Cel, TomaszX
> Sent: Thursday, October 4, 2018 12:22 PM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; akhil.goyal@nxp.com; Kovacevic, Marko
> <marko.kovacevic@intel.com>; Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>; Cel, TomaszX
> <tomaszx.cel@intel.com>
> Subject: [PATCH v2 0/3] add AES-CMAC support
>
> This patch add support, update QAT documentation and enable tests for AES-CMAC.
>
> v2:
> * deleted unnecessary white signs from documentation part
>
> Tomasz Cel (3):
> crypto/qat: add support AES-CMAC
> test/qat: test for AES-CMAC
> doc/qat: add AES-CMAC to the QAT feature list
>
> doc/guides/cryptodevs/features/qat.ini | 1 +
> drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++--------
> drivers/crypto/qat/qat_sym_session.h | 3 +
> test/test/test_cryptodev_hash_test_vectors.h | 12 +-
> 4 files changed, 148 insertions(+), 58 deletions(-)
Series-acked-by: Fiona Trahe <fiona.trahe@intel.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [dpdk-stable] [dpdk-dev] [PATCH v2 1/3] crypto/qat: add support AES-CMAC
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
@ 2018-10-05 12:02 ` Mattias Rönnblom
0 siblings, 0 replies; 21+ messages in thread
From: Mattias Rönnblom @ 2018-10-05 12:02 UTC (permalink / raw)
To: Tomasz Cel, dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic, arkadiuszx.kusztal
You will also need to update drivers/crypto/qat/qat_sym_capabilities.h
with AES CMAC, so that rte_cryptodev_sym_capability_* works as expected.
Regards,
Mattias
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v3 0/3] add AES-CMAC support
2018-09-28 18:10 [dpdk-stable] [PATCH 0/3] add AES-CMAC support Tomasz Cel
` (3 preceding siblings ...)
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Tomasz Cel
@ 2018-10-08 17:16 ` Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
` (2 more replies)
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Tomasz Cel
5 siblings, 3 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-08 17:16 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, mattias.ronnblom, Tomasz Cel
This patch add support for AES-CMAC, moreover update QAT documentation
and enable tests for AES-CMAC.
v2:
* deleted unnecessary white signs from documentation part
v3:
* added AES-CMAC to the capabilities list
* updated release note for 18.11
* updated qat.rst file
Tomasz Cel (3):
crypto/qat: add support AES-CMAC
test/qat: test for AES-CMAC
doc/qat: update AES-CMAC documentation
doc/guides/cryptodevs/features/qat.ini | 1 +
doc/guides/cryptodevs/qat.rst | 1 +
doc/guides/rel_notes/release_18_11.rst | 6 +
drivers/crypto/qat/qat_sym_capabilities.h | 20 +++
drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++--------
drivers/crypto/qat/qat_sym_session.h | 3 +
test/test/test_cryptodev_hash_test_vectors.h | 12 +-
7 files changed, 175 insertions(+), 58 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v3 1/3] crypto/qat: add support AES-CMAC
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 " Tomasz Cel
@ 2018-10-08 17:16 ` Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 2/3] test/qat: test for AES-CMAC Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 3/3] doc/qat: update AES-CMAC documentation Tomasz Cel
2 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-08 17:16 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, mattias.ronnblom, Tomasz Cel
This patch add AES-CMAC support. CMAC is a keyed hash function
that is based on a symmetric key block cipher. It is One-Key
CBC MAC improvement over XCBC-MAC. RFC 4493. NIST SP 800-38B.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++++++++----------
drivers/crypto/qat/qat_sym_session.h | 3 +
2 files changed, 139 insertions(+), 54 deletions(-)
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 1d58220..8196e23 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -498,6 +498,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
struct qat_sym_dev_private *internals = dev->data->dev_private;
uint8_t *key_data = auth_xform->key.data;
uint8_t key_length = auth_xform->key.length;
+ session->aes_cmac = 0;
switch (auth_xform->algo) {
case RTE_CRYPTO_AUTH_SHA1_HMAC:
@@ -518,6 +519,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
break;
+ case RTE_CRYPTO_AUTH_AES_CMAC:
+ session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
+ session->aes_cmac = 1;
+ break;
case RTE_CRYPTO_AUTH_AES_GMAC:
if (qat_sym_validate_aes_key(auth_xform->key.length,
&session->qat_cipher_alg) != 0) {
@@ -555,7 +560,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
case RTE_CRYPTO_AUTH_SHA224:
case RTE_CRYPTO_AUTH_SHA384:
case RTE_CRYPTO_AUTH_MD5:
- case RTE_CRYPTO_AUTH_AES_CMAC:
case RTE_CRYPTO_AUTH_AES_CBC_MAC:
QAT_LOG(ERR, "Crypto: Unsupported hash alg %u",
auth_xform->algo);
@@ -817,6 +821,8 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
return ICP_QAT_HW_SHA512_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
return ICP_QAT_HW_MD5_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
+ return ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum digest size in this case */
return ICP_QAT_HW_SHA512_STATE1_SZ;
@@ -843,6 +849,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
return SHA512_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
return 16;
+ case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
+ return ICP_QAT_HW_AES_BLK_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
return MD5_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
@@ -991,11 +999,28 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
#define HMAC_OPAD_VALUE 0x5c
#define HASH_XCBC_PRECOMP_KEY_NUM 3
+static const uint8_t AES_CMAC_SEED[ICP_QAT_HW_AES_128_KEY_SZ];
+
+static void aes_cmac_key_derive(uint8_t *base, uint8_t *derived)
+{
+ int i;
+
+ derived[0] = base[0] << 1;
+ for (i = 1; i < ICP_QAT_HW_AES_BLK_SZ ; i++) {
+ derived[i] = base[i] << 1;
+ derived[i - 1] |= base[i] >> 7;
+ }
+
+ if (base[0] & 0x80)
+ derived[ICP_QAT_HW_AES_BLK_SZ - 1] ^= QAT_AES_CMAC_CONST_RB;
+}
+
static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
const uint8_t *auth_key,
uint16_t auth_keylen,
uint8_t *p_state_buf,
- uint16_t *p_state_len)
+ uint16_t *p_state_len,
+ uint8_t aes_cmac)
{
int block_size;
uint8_t ipad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
@@ -1003,47 +1028,91 @@ static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
int i;
if (hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC) {
- static uint8_t qat_aes_xcbc_key_seed[
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- };
- uint8_t *in = NULL;
- uint8_t *out = p_state_buf;
- int x;
- AES_KEY enc_key;
+ /* CMAC */
+ if (aes_cmac) {
+ AES_KEY enc_key;
+ uint8_t *in = NULL;
+ uint8_t k0[ICP_QAT_HW_AES_128_KEY_SZ];
+ uint8_t *k1, *k2;
- in = rte_zmalloc("working mem for key",
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
- if (in == NULL) {
- QAT_LOG(ERR, "Failed to alloc memory");
- return -ENOMEM;
- }
+ auth_keylen = ICP_QAT_HW_AES_128_KEY_SZ;
+
+ in = rte_zmalloc("AES CMAC K1",
+ ICP_QAT_HW_AES_128_KEY_SZ, 16);
+
+ if (in == NULL) {
+ QAT_LOG(ERR, "Failed to alloc memory");
+ return -ENOMEM;
+ }
+
+ rte_memcpy(in, AES_CMAC_SEED,
+ ICP_QAT_HW_AES_128_KEY_SZ);
+ rte_memcpy(p_state_buf, auth_key, auth_keylen);
- rte_memcpy(in, qat_aes_xcbc_key_seed,
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
- for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
&enc_key) != 0) {
- rte_free(in -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
- memset(out -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
- 0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ rte_free(in);
return -EFAULT;
}
- AES_encrypt(in, out, &enc_key);
- in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
- out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+
+ AES_encrypt(in, k0, &enc_key);
+
+ k1 = p_state_buf + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+ k2 = k1 + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+
+ aes_cmac_key_derive(k0, k1);
+ aes_cmac_key_derive(k1, k2);
+
+ memset(k0, 0, ICP_QAT_HW_AES_128_KEY_SZ);
+ *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
+ rte_free(in);
+ return 0;
+ } else {
+ static uint8_t qat_aes_xcbc_key_seed[
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ };
+
+ uint8_t *in = NULL;
+ uint8_t *out = p_state_buf;
+ int x;
+ AES_KEY enc_key;
+
+ in = rte_zmalloc("working mem for key",
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
+ if (in == NULL) {
+ QAT_LOG(ERR, "Failed to alloc memory");
+ return -ENOMEM;
+ }
+
+ rte_memcpy(in, qat_aes_xcbc_key_seed,
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
+ if (AES_set_encrypt_key(auth_key,
+ auth_keylen << 3,
+ &enc_key) != 0) {
+ rte_free(in -
+ (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
+ memset(out -
+ (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
+ 0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ return -EFAULT;
+ }
+ AES_encrypt(in, out, &enc_key);
+ in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+ out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+ }
+ *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
+ rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
+ return 0;
}
- *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
- rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
- return 0;
+
} else if ((hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
(hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
uint8_t *in = NULL;
@@ -1417,7 +1486,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9
- || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3)
+ || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3
+ || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC
+ )
hash->auth_counter.counter = 0;
else
hash->auth_counter.counter = rte_bswap32(
@@ -1430,40 +1501,45 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
*/
switch (cdesc->qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
break;
case ICP_QAT_HW_AUTH_ALGO_SHA224:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA384:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
@@ -1471,10 +1547,16 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
break;
case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
state1_size = ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+
+ if (cdesc->aes_cmac)
+ memset(cdesc->cd_cur_ptr, 0, state1_size);
if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC,
authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size)) {
- QAT_LOG(ERR, "(XCBC)precompute failed");
+ &state2_size, cdesc->aes_cmac)) {
+ cdesc->aes_cmac ? QAT_LOG(ERR,
+ "(CMAC)precompute failed")
+ : QAT_LOG(ERR,
+ "(XCBC)precompute failed");
return -EFAULT;
}
break;
@@ -1482,9 +1564,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;
state1_size = ICP_QAT_HW_GALOIS_128_STATE1_SZ;
- if (qat_sym_do_precomputes(cdesc->qat_hash_alg,
- authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size)) {
+ if (qat_sym_do_precomputes(cdesc->qat_hash_alg, authkey,
+ authkeylen, cdesc->cd_cur_ptr + state1_size,
+ &state2_size, cdesc->aes_cmac)) {
QAT_LOG(ERR, "(GCM)precompute failed");
return -EFAULT;
}
@@ -1542,9 +1624,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
break;
case ICP_QAT_HW_AUTH_ALGO_MD5:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5,
- authkey, authkeylen, cdesc->cd_cur_ptr,
- &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(MD5)precompute failed");
return -EFAULT;
}
diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h
index e8f51e5..43e25ce 100644
--- a/drivers/crypto/qat/qat_sym_session.h
+++ b/drivers/crypto/qat/qat_sym_session.h
@@ -36,6 +36,8 @@
ICP_QAT_HW_CIPHER_KEY_CONVERT, \
ICP_QAT_HW_CIPHER_DECRYPT)
+#define QAT_AES_CMAC_CONST_RB 0x87
+
enum qat_sym_proto_flag {
QAT_CRYPTO_PROTO_FLAG_NONE = 0,
QAT_CRYPTO_PROTO_FLAG_CCM = 1,
@@ -75,6 +77,7 @@ struct qat_sym_session {
uint16_t digest_length;
rte_spinlock_t lock; /* protects this struct */
enum qat_device_gen min_qat_dev_gen;
+ uint8_t aes_cmac;
};
int
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v3 2/3] test/qat: test for AES-CMAC
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 " Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
@ 2018-10-08 17:16 ` Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 3/3] doc/qat: update AES-CMAC documentation Tomasz Cel
2 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-08 17:16 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, mattias.ronnblom, Tomasz Cel
Enable tests for AES-CMAC authentication algorithm.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
---
test/test/test_cryptodev_hash_test_vectors.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/test/test/test_cryptodev_hash_test_vectors.h b/test/test/test_cryptodev_hash_test_vectors.h
index cf86dbb..8b6349c 100644
--- a/test/test/test_cryptodev_hash_test_vectors.h
+++ b/test/test/test_cryptodev_hash_test_vectors.h
@@ -634,25 +634,29 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.test_descr = "CMAC Digest 12B",
.test_data = &cmac_test_vector_12,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest Verify 12B",
.test_data = &cmac_test_vector_12,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest 16B",
.test_data = &cmac_test_vector,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest Verify 16B",
.test_data = &cmac_test_vector,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
}
};
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v3 3/3] doc/qat: update AES-CMAC documentation
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 " Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 2/3] test/qat: test for AES-CMAC Tomasz Cel
@ 2018-10-08 17:16 ` Tomasz Cel
2018-10-09 14:37 ` Trahe, Fiona
2 siblings, 1 reply; 21+ messages in thread
From: Tomasz Cel @ 2018-10-08 17:16 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, mattias.ronnblom, Tomasz Cel
Update the QAT documentation to show that it supports AES-CMAC.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
---
doc/guides/cryptodevs/features/qat.ini | 1 +
doc/guides/cryptodevs/qat.rst | 1 +
doc/guides/rel_notes/release_18_11.rst | 6 ++++++
drivers/crypto/qat/qat_sym_capabilities.h | 20 ++++++++++++++++++++
4 files changed, 28 insertions(+)
diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini
index 220291b..4f15ee0 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -48,6 +48,7 @@ SNOW3G UIA2 = Y
KASUMI F9 = Y
AES XCBC MAC = Y
ZUC EIA3 = Y
+AES CMAC (128) = Y
;
; Supported AEAD algorithms of the 'qat' crypto driver.
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index b09624f..d1d4833 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -62,6 +62,7 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_KASUMI_F9``
* ``RTE_CRYPTO_AUTH_AES_GMAC``
* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+* ``RTE_CRYPTO_AUTH_AES_CMAC``
Supported AEAD algorithms:
diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst
index 2133a5b..18a39a8 100644
--- a/doc/guides/rel_notes/release_18_11.rst
+++ b/doc/guides/rel_notes/release_18_11.rst
@@ -72,6 +72,12 @@ New Features
SR-IOV option in Hyper-V and Azure. This is an alternative to the previous
vdev_netvsc, tap, and failsafe drivers combination.
+* **Updated the QAT PMD.**
+
+ The QAT PMD was updated with additional support for:
+
+ * AES-CMAC algorithm.
+
* **Updated failsafe driver.**
Updated the failsafe driver including the following changes:
diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h
index eea08bc..7cba87d 100644
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -154,6 +154,26 @@
}, } \
}, } \
}, \
+ { /* AES CMAC */ \
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+ {.sym = { \
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, \
+ {.auth = { \
+ .algo = RTE_CRYPTO_AUTH_AES_CMAC, \
+ .block_size = 16, \
+ .key_size = { \
+ .min = 16, \
+ .max = 16, \
+ .increment = 0 \
+ }, \
+ .digest_size = { \
+ .min = 12, \
+ .max = 16, \
+ .increment = 4 \
+ } \
+ }, } \
+ }, } \
+ }, \
{ /* AES CCM */ \
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
{.sym = { \
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [dpdk-stable] [PATCH v3 3/3] doc/qat: update AES-CMAC documentation
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 3/3] doc/qat: update AES-CMAC documentation Tomasz Cel
@ 2018-10-09 14:37 ` Trahe, Fiona
0 siblings, 0 replies; 21+ messages in thread
From: Trahe, Fiona @ 2018-10-09 14:37 UTC (permalink / raw)
To: Cel, TomaszX, dev
Cc: stable, akhil.goyal, Kovacevic, Marko, Kusztal, ArkadiuszX,
mattias.ronnblom, Trahe, Fiona
> -----Original Message-----
> From: Cel, TomaszX
> Sent: Monday, October 8, 2018 6:17 PM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; akhil.goyal@nxp.com; Kovacevic, Marko
> <marko.kovacevic@intel.com>; Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>;
> mattias.ronnblom@ericsson.com; Cel, TomaszX <tomaszx.cel@intel.com>
> Subject: [PATCH v3 3/3] doc/qat: update AES-CMAC documentation
>
> Update the QAT documentation to show that it supports AES-CMAC.
>
> Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
Nack.
The capabilities change should be in the PMD patch 1/3
We'll send a v4 shortly.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support
2018-09-28 18:10 [dpdk-stable] [PATCH 0/3] add AES-CMAC support Tomasz Cel
` (4 preceding siblings ...)
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 " Tomasz Cel
@ 2018-10-09 16:08 ` Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
` (3 more replies)
5 siblings, 4 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-09 16:08 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, mattias.ronnblom, Tomasz Cel
This patch add support for AES-CMAC, moreover update QAT documentation
and enable tests for AES-CMAC.
v4:
- moved the capability changes from patch doc/qat to patch crypto/qat
v3:
- added AES-CMAC to the capabilities list
- updated release note for 18.11
- updated qat.rst file
v2:
- deleted unnecessary white space from documentation part
Tomasz Cel (3):
crypto/qat: add support AES-CMAC
test/qat: test for AES-CMAC
doc/qat: update AES-CMAC documentation
doc/guides/cryptodevs/features/qat.ini | 1 +
doc/guides/cryptodevs/qat.rst | 1 +
doc/guides/rel_notes/release_18_11.rst | 6 +
drivers/crypto/qat/qat_sym_capabilities.h | 20 +++
drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++--------
drivers/crypto/qat/qat_sym_session.h | 3 +
test/test/test_cryptodev_hash_test_vectors.h | 12 +-
7 files changed, 175 insertions(+), 58 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v4 1/3] crypto/qat: add support AES-CMAC
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Tomasz Cel
@ 2018-10-09 16:08 ` Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 2/3] test/qat: test for AES-CMAC Tomasz Cel
` (2 subsequent siblings)
3 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-09 16:08 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, mattias.ronnblom, Tomasz Cel
This patch add AES-CMAC support. CMAC is a keyed hash function
that is based on a symmetric key block cipher. It is One-Key
CBC MAC improvement over XCBC-MAC. RFC 4493. NIST SP 800-38B.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
drivers/crypto/qat/qat_sym_capabilities.h | 20 ++++
drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++++---------
drivers/crypto/qat/qat_sym_session.h | 3 +
3 files changed, 159 insertions(+), 54 deletions(-)
diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h
index eea08bc..7cba87d 100644
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -154,6 +154,26 @@
}, } \
}, } \
}, \
+ { /* AES CMAC */ \
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+ {.sym = { \
+ .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, \
+ {.auth = { \
+ .algo = RTE_CRYPTO_AUTH_AES_CMAC, \
+ .block_size = 16, \
+ .key_size = { \
+ .min = 16, \
+ .max = 16, \
+ .increment = 0 \
+ }, \
+ .digest_size = { \
+ .min = 12, \
+ .max = 16, \
+ .increment = 4 \
+ } \
+ }, } \
+ }, } \
+ }, \
{ /* AES CCM */ \
.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
{.sym = { \
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 1d58220..8196e23 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -498,6 +498,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
struct qat_sym_dev_private *internals = dev->data->dev_private;
uint8_t *key_data = auth_xform->key.data;
uint8_t key_length = auth_xform->key.length;
+ session->aes_cmac = 0;
switch (auth_xform->algo) {
case RTE_CRYPTO_AUTH_SHA1_HMAC:
@@ -518,6 +519,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
break;
+ case RTE_CRYPTO_AUTH_AES_CMAC:
+ session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
+ session->aes_cmac = 1;
+ break;
case RTE_CRYPTO_AUTH_AES_GMAC:
if (qat_sym_validate_aes_key(auth_xform->key.length,
&session->qat_cipher_alg) != 0) {
@@ -555,7 +560,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
case RTE_CRYPTO_AUTH_SHA224:
case RTE_CRYPTO_AUTH_SHA384:
case RTE_CRYPTO_AUTH_MD5:
- case RTE_CRYPTO_AUTH_AES_CMAC:
case RTE_CRYPTO_AUTH_AES_CBC_MAC:
QAT_LOG(ERR, "Crypto: Unsupported hash alg %u",
auth_xform->algo);
@@ -817,6 +821,8 @@ static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)
return ICP_QAT_HW_SHA512_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
return ICP_QAT_HW_MD5_STATE1_SZ;
+ case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
+ return ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
/* return maximum digest size in this case */
return ICP_QAT_HW_SHA512_STATE1_SZ;
@@ -843,6 +849,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)
return SHA512_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_GALOIS_128:
return 16;
+ case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
+ return ICP_QAT_HW_AES_BLK_SZ;
case ICP_QAT_HW_AUTH_ALGO_MD5:
return MD5_CBLOCK;
case ICP_QAT_HW_AUTH_ALGO_DELIMITER:
@@ -991,11 +999,28 @@ static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,
#define HMAC_OPAD_VALUE 0x5c
#define HASH_XCBC_PRECOMP_KEY_NUM 3
+static const uint8_t AES_CMAC_SEED[ICP_QAT_HW_AES_128_KEY_SZ];
+
+static void aes_cmac_key_derive(uint8_t *base, uint8_t *derived)
+{
+ int i;
+
+ derived[0] = base[0] << 1;
+ for (i = 1; i < ICP_QAT_HW_AES_BLK_SZ ; i++) {
+ derived[i] = base[i] << 1;
+ derived[i - 1] |= base[i] >> 7;
+ }
+
+ if (base[0] & 0x80)
+ derived[ICP_QAT_HW_AES_BLK_SZ - 1] ^= QAT_AES_CMAC_CONST_RB;
+}
+
static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
const uint8_t *auth_key,
uint16_t auth_keylen,
uint8_t *p_state_buf,
- uint16_t *p_state_len)
+ uint16_t *p_state_len,
+ uint8_t aes_cmac)
{
int block_size;
uint8_t ipad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];
@@ -1003,47 +1028,91 @@ static int qat_sym_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,
int i;
if (hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC) {
- static uint8_t qat_aes_xcbc_key_seed[
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
- };
- uint8_t *in = NULL;
- uint8_t *out = p_state_buf;
- int x;
- AES_KEY enc_key;
+ /* CMAC */
+ if (aes_cmac) {
+ AES_KEY enc_key;
+ uint8_t *in = NULL;
+ uint8_t k0[ICP_QAT_HW_AES_128_KEY_SZ];
+ uint8_t *k1, *k2;
- in = rte_zmalloc("working mem for key",
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
- if (in == NULL) {
- QAT_LOG(ERR, "Failed to alloc memory");
- return -ENOMEM;
- }
+ auth_keylen = ICP_QAT_HW_AES_128_KEY_SZ;
+
+ in = rte_zmalloc("AES CMAC K1",
+ ICP_QAT_HW_AES_128_KEY_SZ, 16);
+
+ if (in == NULL) {
+ QAT_LOG(ERR, "Failed to alloc memory");
+ return -ENOMEM;
+ }
+
+ rte_memcpy(in, AES_CMAC_SEED,
+ ICP_QAT_HW_AES_128_KEY_SZ);
+ rte_memcpy(p_state_buf, auth_key, auth_keylen);
- rte_memcpy(in, qat_aes_xcbc_key_seed,
- ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
- for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
if (AES_set_encrypt_key(auth_key, auth_keylen << 3,
&enc_key) != 0) {
- rte_free(in -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
- memset(out -
- (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
- 0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ rte_free(in);
return -EFAULT;
}
- AES_encrypt(in, out, &enc_key);
- in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
- out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+
+ AES_encrypt(in, k0, &enc_key);
+
+ k1 = p_state_buf + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+ k2 = k1 + ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+
+ aes_cmac_key_derive(k0, k1);
+ aes_cmac_key_derive(k1, k2);
+
+ memset(k0, 0, ICP_QAT_HW_AES_128_KEY_SZ);
+ *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
+ rte_free(in);
+ return 0;
+ } else {
+ static uint8_t qat_aes_xcbc_key_seed[
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ };
+
+ uint8_t *in = NULL;
+ uint8_t *out = p_state_buf;
+ int x;
+ AES_KEY enc_key;
+
+ in = rte_zmalloc("working mem for key",
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);
+ if (in == NULL) {
+ QAT_LOG(ERR, "Failed to alloc memory");
+ return -ENOMEM;
+ }
+
+ rte_memcpy(in, qat_aes_xcbc_key_seed,
+ ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ for (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {
+ if (AES_set_encrypt_key(auth_key,
+ auth_keylen << 3,
+ &enc_key) != 0) {
+ rte_free(in -
+ (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ));
+ memset(out -
+ (x * ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ),
+ 0, ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);
+ return -EFAULT;
+ }
+ AES_encrypt(in, out, &enc_key);
+ in += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+ out += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;
+ }
+ *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
+ rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
+ return 0;
}
- *p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;
- rte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);
- return 0;
+
} else if ((hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
(hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
uint8_t *in = NULL;
@@ -1417,7 +1486,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
if (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2
|| cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9
- || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3)
+ || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3
+ || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC
+ )
hash->auth_counter.counter = 0;
else
hash->auth_counter.counter = rte_bswap32(
@@ -1430,40 +1501,45 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
*/
switch (cdesc->qat_hash_alg) {
case ICP_QAT_HW_AUTH_ALGO_SHA1:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA1, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = RTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);
break;
case ICP_QAT_HW_AUTH_ALGO_SHA224:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA224, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA224_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA256:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA256, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA256_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA384:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA384, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
state2_size = ICP_QAT_HW_SHA384_STATE2_SZ;
break;
case ICP_QAT_HW_AUTH_ALGO_SHA512:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512,
- authkey, authkeylen, cdesc->cd_cur_ptr, &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_SHA512, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(SHA)precompute failed");
return -EFAULT;
}
@@ -1471,10 +1547,16 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
break;
case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:
state1_size = ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;
+
+ if (cdesc->aes_cmac)
+ memset(cdesc->cd_cur_ptr, 0, state1_size);
if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC,
authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size)) {
- QAT_LOG(ERR, "(XCBC)precompute failed");
+ &state2_size, cdesc->aes_cmac)) {
+ cdesc->aes_cmac ? QAT_LOG(ERR,
+ "(CMAC)precompute failed")
+ : QAT_LOG(ERR,
+ "(XCBC)precompute failed");
return -EFAULT;
}
break;
@@ -1482,9 +1564,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
case ICP_QAT_HW_AUTH_ALGO_GALOIS_64:
qat_proto_flag = QAT_CRYPTO_PROTO_FLAG_GCM;
state1_size = ICP_QAT_HW_GALOIS_128_STATE1_SZ;
- if (qat_sym_do_precomputes(cdesc->qat_hash_alg,
- authkey, authkeylen, cdesc->cd_cur_ptr + state1_size,
- &state2_size)) {
+ if (qat_sym_do_precomputes(cdesc->qat_hash_alg, authkey,
+ authkeylen, cdesc->cd_cur_ptr + state1_size,
+ &state2_size, cdesc->aes_cmac)) {
QAT_LOG(ERR, "(GCM)precompute failed");
return -EFAULT;
}
@@ -1542,9 +1624,9 @@ int qat_sym_session_aead_create_cd_auth(struct qat_sym_session *cdesc,
break;
case ICP_QAT_HW_AUTH_ALGO_MD5:
- if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5,
- authkey, authkeylen, cdesc->cd_cur_ptr,
- &state1_size)) {
+ if (qat_sym_do_precomputes(ICP_QAT_HW_AUTH_ALGO_MD5, authkey,
+ authkeylen, cdesc->cd_cur_ptr, &state1_size,
+ cdesc->aes_cmac)) {
QAT_LOG(ERR, "(MD5)precompute failed");
return -EFAULT;
}
diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h
index e8f51e5..43e25ce 100644
--- a/drivers/crypto/qat/qat_sym_session.h
+++ b/drivers/crypto/qat/qat_sym_session.h
@@ -36,6 +36,8 @@
ICP_QAT_HW_CIPHER_KEY_CONVERT, \
ICP_QAT_HW_CIPHER_DECRYPT)
+#define QAT_AES_CMAC_CONST_RB 0x87
+
enum qat_sym_proto_flag {
QAT_CRYPTO_PROTO_FLAG_NONE = 0,
QAT_CRYPTO_PROTO_FLAG_CCM = 1,
@@ -75,6 +77,7 @@ struct qat_sym_session {
uint16_t digest_length;
rte_spinlock_t lock; /* protects this struct */
enum qat_device_gen min_qat_dev_gen;
+ uint8_t aes_cmac;
};
int
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v4 2/3] test/qat: test for AES-CMAC
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
@ 2018-10-09 16:08 ` Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 3/3] doc/qat: update AES-CMAC documentation Tomasz Cel
2018-10-09 16:25 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Trahe, Fiona
3 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-09 16:08 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, mattias.ronnblom, Tomasz Cel
Enable tests for AES-CMAC authentication algorithm.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
---
test/test/test_cryptodev_hash_test_vectors.h | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/test/test/test_cryptodev_hash_test_vectors.h b/test/test/test_cryptodev_hash_test_vectors.h
index c430409..af1e29e 100644
--- a/test/test/test_cryptodev_hash_test_vectors.h
+++ b/test/test/test_cryptodev_hash_test_vectors.h
@@ -660,25 +660,29 @@ static const struct blockcipher_test_case hash_test_cases[] = {
.test_descr = "CMAC Digest 12B",
.test_data = &cmac_test_vector_12,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest Verify 12B",
.test_data = &cmac_test_vector_12,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest 16B",
.test_data = &cmac_test_vector,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_GEN,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
},
{
.test_descr = "CMAC Digest Verify 16B",
.test_data = &cmac_test_vector,
.op_mask = BLOCKCIPHER_TEST_OP_AUTH_VERIFY,
- .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB
+ .pmd_mask = BLOCKCIPHER_TEST_TARGET_PMD_MB |
+ BLOCKCIPHER_TEST_TARGET_PMD_QAT
}
};
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-stable] [PATCH v4 3/3] doc/qat: update AES-CMAC documentation
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 2/3] test/qat: test for AES-CMAC Tomasz Cel
@ 2018-10-09 16:08 ` Tomasz Cel
2018-10-09 16:25 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Trahe, Fiona
3 siblings, 0 replies; 21+ messages in thread
From: Tomasz Cel @ 2018-10-09 16:08 UTC (permalink / raw)
To: dev
Cc: stable, fiona.trahe, akhil.goyal, marko.kovacevic,
arkadiuszx.kusztal, mattias.ronnblom, Tomasz Cel
Update the QAT documentation to show that it supports AES-CMAC.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
---
doc/guides/cryptodevs/features/qat.ini | 1 +
doc/guides/cryptodevs/qat.rst | 1 +
doc/guides/rel_notes/release_18_11.rst | 6 ++++++
3 files changed, 8 insertions(+)
diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini
index 220291b..4f15ee0 100644
--- a/doc/guides/cryptodevs/features/qat.ini
+++ b/doc/guides/cryptodevs/features/qat.ini
@@ -48,6 +48,7 @@ SNOW3G UIA2 = Y
KASUMI F9 = Y
AES XCBC MAC = Y
ZUC EIA3 = Y
+AES CMAC (128) = Y
;
; Supported AEAD algorithms of the 'qat' crypto driver.
diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index b09624f..d1d4833 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -62,6 +62,7 @@ Hash algorithms:
* ``RTE_CRYPTO_AUTH_KASUMI_F9``
* ``RTE_CRYPTO_AUTH_AES_GMAC``
* ``RTE_CRYPTO_AUTH_ZUC_EIA3``
+* ``RTE_CRYPTO_AUTH_AES_CMAC``
Supported AEAD algorithms:
diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst
index 2133a5b..18a39a8 100644
--- a/doc/guides/rel_notes/release_18_11.rst
+++ b/doc/guides/rel_notes/release_18_11.rst
@@ -72,6 +72,12 @@ New Features
SR-IOV option in Hyper-V and Azure. This is an alternative to the previous
vdev_netvsc, tap, and failsafe drivers combination.
+* **Updated the QAT PMD.**
+
+ The QAT PMD was updated with additional support for:
+
+ * AES-CMAC algorithm.
+
* **Updated failsafe driver.**
Updated the failsafe driver including the following changes:
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Tomasz Cel
` (2 preceding siblings ...)
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 3/3] doc/qat: update AES-CMAC documentation Tomasz Cel
@ 2018-10-09 16:25 ` Trahe, Fiona
2018-10-10 10:59 ` [dpdk-stable] [dpdk-dev] " Akhil Goyal
3 siblings, 1 reply; 21+ messages in thread
From: Trahe, Fiona @ 2018-10-09 16:25 UTC (permalink / raw)
To: Cel, TomaszX, dev
Cc: stable, akhil.goyal, Kovacevic, Marko, Kusztal, ArkadiuszX,
mattias.ronnblom
> -----Original Message-----
> From: Cel, TomaszX
> Sent: Tuesday, October 9, 2018 5:08 PM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; akhil.goyal@nxp.com; Kovacevic, Marko
> <marko.kovacevic@intel.com>; Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>;
> mattias.ronnblom@ericsson.com; Cel, TomaszX <tomaszx.cel@intel.com>
> Subject: [PATCH v4 0/3] add AES-CMAC support
>
> This patch add support for AES-CMAC, moreover update QAT documentation
> and enable tests for AES-CMAC.
>
> v4:
> - moved the capability changes from patch doc/qat to patch crypto/qat
>
> v3:
> - added AES-CMAC to the capabilities list
> - updated release note for 18.11
> - updated qat.rst file
>
> v2:
> - deleted unnecessary white space from documentation part
>
> Tomasz Cel (3):
> crypto/qat: add support AES-CMAC
> test/qat: test for AES-CMAC
> doc/qat: update AES-CMAC documentation
>
> doc/guides/cryptodevs/features/qat.ini | 1 +
> doc/guides/cryptodevs/qat.rst | 1 +
> doc/guides/rel_notes/release_18_11.rst | 6 +
> drivers/crypto/qat/qat_sym_capabilities.h | 20 +++
> drivers/crypto/qat/qat_sym_session.c | 190 +++++++++++++++++++--------
> drivers/crypto/qat/qat_sym_session.h | 3 +
> test/test/test_cryptodev_hash_test_vectors.h | 12 +-
> 7 files changed, 175 insertions(+), 58 deletions(-)
>
> --
> 2.7.4
Series-acked-by: Fiona Trahe <fiona.trahe@intel.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [dpdk-stable] [dpdk-dev] [PATCH v4 0/3] add AES-CMAC support
2018-10-09 16:25 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Trahe, Fiona
@ 2018-10-10 10:59 ` Akhil Goyal
0 siblings, 0 replies; 21+ messages in thread
From: Akhil Goyal @ 2018-10-10 10:59 UTC (permalink / raw)
To: Trahe, Fiona, Cel, TomaszX, dev
Cc: stable, Kovacevic, Marko, Kusztal, ArkadiuszX, mattias.ronnblom
On 10/9/2018 9:55 PM, Trahe, Fiona wrote:
> acked-by: Fiona Trahe<fiona.trahe@intel.com>
Applied to dpdk-next-crypto
Thanks
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2018-10-10 10:59 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-09-28 18:10 [dpdk-stable] [PATCH 0/3] add AES-CMAC support Tomasz Cel
2018-09-28 18:10 ` [dpdk-stable] [PATCH 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
2018-09-28 18:10 ` [dpdk-stable] [PATCH 2/3] test/qat: test for AES-CMAC Tomasz Cel
2018-09-28 18:10 ` [dpdk-stable] [PATCH 3/3] doc/qat: add AES-CMAC to the QAT feature list Tomasz Cel
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Tomasz Cel
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
2018-10-05 12:02 ` [dpdk-stable] [dpdk-dev] " Mattias Rönnblom
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 2/3] test/qat: test for AES-CMAC Tomasz Cel
2018-10-04 11:22 ` [dpdk-stable] [PATCH v2 3/3] doc/qat: add AES-CMAC to the QAT feature list Tomasz Cel
2018-10-04 11:47 ` [dpdk-stable] [PATCH v2 0/3] add AES-CMAC support Trahe, Fiona
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 " Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 2/3] test/qat: test for AES-CMAC Tomasz Cel
2018-10-08 17:16 ` [dpdk-stable] [PATCH v3 3/3] doc/qat: update AES-CMAC documentation Tomasz Cel
2018-10-09 14:37 ` Trahe, Fiona
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 1/3] crypto/qat: add support AES-CMAC Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 2/3] test/qat: test for AES-CMAC Tomasz Cel
2018-10-09 16:08 ` [dpdk-stable] [PATCH v4 3/3] doc/qat: update AES-CMAC documentation Tomasz Cel
2018-10-09 16:25 ` [dpdk-stable] [PATCH v4 0/3] add AES-CMAC support Trahe, Fiona
2018-10-10 10:59 ` [dpdk-stable] [dpdk-dev] " Akhil Goyal
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