[dpdk-stable] [PATCH 17.11 1/5] net/qede/base: fix MFW FLR flow

[dpdk-stable] [PATCH 17.11 1/5] net/qede/base: fix MFW FLR flow

[Mody, Rasesh]

From: Shahed Shaikh <shahed.shaikh@cavium.com>

[ backported from upstream commit 797ce8eec7c1b9e37dd9398403e9bc888cca0013 ]

Management firmware does not properly clean IGU block in PF FLR flow
which may result in undelivered attentions for link events from
default status block.
Add a workaround in PMD to execute extra IGU cleanup right after PF FLR
is done.

Fixes: 9e2f08a4ad5f ("net/qede/base: add request for PF FLR before load request")

Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>
---
 drivers/net/qede/base/ecore_dev.c  |    7 +++++++
 drivers/net/qede/base/ecore_int.c  |   32 ++++++++++++++++++++++++++++++++
 drivers/net/qede/base/ecore_int.h  |    1 +
 drivers/net/qede/base/mcp_public.h |    2 ++
 drivers/net/qede/base/reg_addr.h   |   15 +++++++++++++++
 5 files changed, 57 insertions(+)

diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 092606b..6a3046d 100644
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -4096,6 +4096,13 @@ void ecore_prepare_hibernate(struct ecore_dev *p_dev)
 		rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
 		if (rc != ECORE_SUCCESS)
 			DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
+
+		/* Workaround for MFW issue where PF FLR does not cleanup
+		 * IGU block
+		 */
+		if (!(p_hwfn->mcp_info->capabilities &
+		      FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
+			ecore_pf_flr_igu_cleanup(p_hwfn);
 	}
 
 	/* Check if mdump logs/data are present and update the epoch value */
diff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c
index 61e36a4..b2582aa 100644
--- a/drivers/net/qede/base/ecore_int.c
+++ b/drivers/net/qede/base/ecore_int.c
@@ -2679,3 +2679,35 @@ enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
 
 	return ECORE_SUCCESS;
 }
+
+void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn)
+{
+	struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
+	struct ecore_ptt *p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
+							     RESERVED_PTT_DPC);
+	int i;
+
+	/* Do not reorder the following cleanup sequence */
+	/* Ack all attentions */
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff);
+
+	/* Clear driver attention */
+	ecore_wr(p_hwfn,  p_dpc_ptt,
+		((p_hwfn->rel_pf_id << 3) + MISC_REG_AEU_GENERAL_ATTN_0), 0);
+
+	/* Clear per-PF IGU registers to restore them as if the IGU
+	 * was reset for this PF
+	 */
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
+
+	/* Execute IGU clean up*/
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1);
+
+	/* Clear Stats */
+	ecore_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED, 0);
+
+	for (i = 0; i < IGU_REG_PBA_STS_PF_SIZE; i++)
+		ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0);
+}
diff --git a/drivers/net/qede/base/ecore_int.h b/drivers/net/qede/base/ecore_int.h
index 563051c..ebee68b 100644
--- a/drivers/net/qede/base/ecore_int.h
+++ b/drivers/net/qede/base/ecore_int.h
@@ -258,4 +258,5 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
 enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
 						   struct ecore_ptt *p_ptt);
 
+void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn);
 #endif /* __ECORE_INT_H__ */
diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h
index 81ca663..b83b241 100644
--- a/drivers/net/qede/base/mcp_public.h
+++ b/drivers/net/qede/base/mcp_public.h
@@ -1777,6 +1777,8 @@ struct public_drv_mb {
 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ   0x00000001
 /* MFW supports EEE */
 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002
+/* MFW support complete IGU cleanup upon FLR */
+#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP	0x00000080
 /* MFW supports virtual link */
 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK       0x00010000
 
diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h
index ad15d28..8f226ad 100644
--- a/drivers/net/qede/base/reg_addr.h
+++ b/drivers/net/qede/base/reg_addr.h
@@ -332,6 +332,21 @@
 	0x180820UL
 #define  IGU_REG_ATTN_MSG_ADDR_H	\
 	0x180824UL
+#define IGU_REG_LEADING_EDGE_LATCH \
+	0x18082cUL
+#define IGU_REG_TRAILING_EDGE_LATCH \
+	0x180830UL
+#define IGU_REG_ATTENTION_ACK_BITS \
+	0x180838UL
+#define IGU_REG_PBA_STS_PF \
+	0x180d20UL
+#define IGU_REG_PF_FUNCTIONAL_CLEANUP \
+	0x181210UL
+#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \
+	0x18042cUL
+#define IGU_REG_PBA_STS_PF_SIZE 5
+#define IGU_REG_PBA_STS_PF \
+	0x180d20UL
 #define  MISC_REG_AEU_GENERAL_ATTN_0 \
 	0x008400UL
 #define  CAU_REG_SB_ADDR_MEMORY \
-- 
1.7.10.3

[dpdk-stable] [PATCH 17.11 2/5] net/qede: fix flow director for IPv6 filter

[Mody, Rasesh]

From: Shahed Shaikh <shahed.shaikh@cavium.com>

[ backported from upstream commit 7ffef6292b6d49fabbbc120663e433442146e263 ]

- PMD does not fill vtc_flow field of IPv6 header while
  constructing a packet for IPv6 filter. Hence filter was
  not getting applied properly.
- IPv6 addresses got swapped while copying src and dst addresses.
- Same issue with UDP and TCP port ids.

Fixes: 622075356e8f ("net/qede: support ntuple and flow director filter")

Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>
---
 drivers/net/qede/qede_fdir.c |   12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/net/qede/qede_fdir.c b/drivers/net/qede/qede_fdir.c
index 0515256..050b737 100644
--- a/drivers/net/qede/qede_fdir.c
+++ b/drivers/net/qede/qede_fdir.c
@@ -18,6 +18,7 @@
 #define QEDE_FDIR_IP_DEFAULT_VERSION_IHL	(IP_VERSION | IP_HDRLEN)
 #define QEDE_FDIR_TCP_DEFAULT_DATAOFF		(0x50)
 #define QEDE_FDIR_IPV4_DEF_TTL			(64)
+#define QEDE_FDIR_IPV6_DEFAULT_VTC_FLOW		(0x60000000)
 
 /* Sum of length of header types of L2, L3, L4.
  * L2 : ether_hdr + vlan_hdr + vxlan_hdr
@@ -340,18 +341,21 @@ void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev)
 		ip6->proto = input->flow.ipv6_flow.proto ?
 					input->flow.ipv6_flow.proto :
 					next_proto[input->flow_type];
-		rte_memcpy(&ip6->src_addr, &input->flow.ipv6_flow.dst_ip,
+		ip6->vtc_flow =
+			rte_cpu_to_be_32(QEDE_FDIR_IPV6_DEFAULT_VTC_FLOW);
+		rte_memcpy(&ip6->src_addr, &input->flow.ipv6_flow.src_ip,
 			   IPV6_ADDR_LEN);
-		rte_memcpy(&ip6->dst_addr, &input->flow.ipv6_flow.src_ip,
+		rte_memcpy(&ip6->dst_addr, &input->flow.ipv6_flow.dst_ip,
 			   IPV6_ADDR_LEN);
 		len += sizeof(struct ipv6_hdr);
+		params->ipv6 = true;
 
 		raw_pkt = (uint8_t *)buff;
 		/* UDP */
 		if (input->flow_type == RTE_ETH_FLOW_NONFRAG_IPV6_UDP) {
 			udp = (struct udp_hdr *)(raw_pkt + len);
-			udp->src_port = input->flow.udp6_flow.dst_port;
-			udp->dst_port = input->flow.udp6_flow.src_port;
+			udp->src_port = input->flow.udp6_flow.src_port;
+			udp->dst_port = input->flow.udp6_flow.dst_port;
 			len += sizeof(struct udp_hdr);
 			params->udp = true;
 		} else { /* TCP */
-- 
1.7.10.3

[dpdk-stable] [PATCH 17.11 3/5] net/qede: fix Rx buffer size calculation

[Mody, Rasesh]

From: Shahed Shaikh <shahed.shaikh@cavium.com>

[ backported from upstream commit 318d7da3122bac04772418c5eda9f50fcd175d18 ]

 - HW does not include CRC in received frame when passed to host,
   so no need to consider CRC length while calculating Rx buffer size.
 - In scattered Rx mode, driver may allocate Rx buffer larger than
   the size of mbuf because it tries to adjust the buffer size to cache
   line size by ceiling it. Fix this by flooring the size instead of
   ceiling.
 - Consider the rule imposed by HW regarding the minimum size of Rx buffer
   in scattered Rx mode -
   (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT

Fixes: f6033f2497e7 ("net/qede: fix minimum buffer size and scatter Rx check")

Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>
---
 drivers/net/qede/qede_ethdev.c |   28 +++++++++----------
 drivers/net/qede/qede_rxtx.c   |   60 +++++++++++++++++++++++++++++++++++-----
 drivers/net/qede/qede_rxtx.h   |   15 ++++++++--
 3 files changed, 79 insertions(+), 24 deletions(-)

diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c
index 4a5e485..1844eea 100644
--- a/drivers/net/qede/qede_ethdev.c
+++ b/drivers/net/qede/qede_ethdev.c
@@ -1383,7 +1383,7 @@ static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 	if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
 		eth_dev->data->mtu =
 				eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
-				ETHER_HDR_LEN - ETHER_CRC_LEN;
+				ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
 
 	if (qede_start_vport(qdev, eth_dev->data->mtu))
 		return -1;
@@ -2377,19 +2377,18 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 	struct qede_fastpath *fp;
 	uint32_t max_rx_pkt_len;
 	uint32_t frame_size;
-	uint16_t rx_buf_size;
 	uint16_t bufsz;
 	bool restart = false;
-	int i;
+	int i, rc;
 
 	PMD_INIT_FUNC_TRACE(edev);
 	qede_dev_info_get(dev, &dev_info);
-	max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
-	frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
+	max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
+	frame_size = max_rx_pkt_len;
 	if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
 		DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
 		       mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
-			ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
+		       QEDE_ETH_OVERHEAD);
 		return -EINVAL;
 	}
 	if (!dev->data->scattered_rx &&
@@ -2417,14 +2416,15 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 		if (fp->rxq != NULL) {
 			bufsz = (uint16_t)rte_pktmbuf_data_room_size(
 				fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
-			if (dev->data->scattered_rx)
-				rx_buf_size = bufsz + ETHER_HDR_LEN +
-					      ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
-			else
-				rx_buf_size = frame_size;
-			rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
-			fp->rxq->rx_buf_size = rx_buf_size;
-			DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
+			/* cache align the mbuf size to simplfy rx_buf_size
+			 * calculation
+			 */
+			bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
+			rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
+			if (rc < 0)
+				return rc;
+
+			fp->rxq->rx_buf_size = rc;
 		}
 	}
 	if (max_rx_pkt_len > ETHER_MAX_LEN)
diff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c
index c88182b..32eae81 100644
--- a/drivers/net/qede/qede_rxtx.c
+++ b/drivers/net/qede/qede_rxtx.c
@@ -37,6 +37,49 @@ static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
 	return 0;
 }
 
+/* Criterias for calculating Rx buffer size -
+ * 1) rx_buf_size should not exceed the size of mbuf
+ * 2) In scattered_rx mode - minimum rx_buf_size should be
+ *    (MTU + Maximum L2 Header Size + 2) / ETH_RX_MAX_BUFF_PER_PKT
+ * 3) In regular mode - minimum rx_buf_size should be
+ *    (MTU + Maximum L2 Header Size + 2)
+ *    In above cases +2 corrosponds to 2 bytes padding in front of L2
+ *    header.
+ * 4) rx_buf_size should be cacheline-size aligned. So considering
+ *    criteria 1, we need to adjust the size to floor instead of ceil,
+ *    so that we don't exceed mbuf size while ceiling rx_buf_size.
+ */
+int
+qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,
+		      uint16_t max_frame_size)
+{
+	struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
+	struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
+	int rx_buf_size;
+
+	if (dev->data->scattered_rx) {
+		/* per HW limitation, only ETH_RX_MAX_BUFF_PER_PKT number of
+		 * bufferes can be used for single packet. So need to make sure
+		 * mbuf size is sufficient enough for this.
+		 */
+		if ((mbufsz * ETH_RX_MAX_BUFF_PER_PKT) <
+		     (max_frame_size + QEDE_ETH_OVERHEAD)) {
+			DP_ERR(edev, "mbuf %d size is not enough to hold max fragments (%d) for max rx packet length (%d)\n",
+			       mbufsz, ETH_RX_MAX_BUFF_PER_PKT, max_frame_size);
+			return -EINVAL;
+		}
+
+		rx_buf_size = RTE_MAX(mbufsz,
+				      (max_frame_size + QEDE_ETH_OVERHEAD) /
+				       ETH_RX_MAX_BUFF_PER_PKT);
+	} else {
+		rx_buf_size = max_frame_size + QEDE_ETH_OVERHEAD;
+	}
+
+	/* Align to cache-line size if needed */
+	return QEDE_FLOOR_TO_CACHE_LINE_SIZE(rx_buf_size);
+}
+
 int
 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 		    uint16_t nb_desc, unsigned int socket_id,
@@ -87,6 +130,9 @@ static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
 
 	/* Fix up RX buffer size */
 	bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
+	/* cache align the mbuf size to simplfy rx_buf_size calculation */
+	bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
+
 	if ((rxmode->enable_scatter)			||
 	    (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
 		if (!dev->data->scattered_rx) {
@@ -95,13 +141,13 @@ static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
 		}
 	}
 
-	if (dev->data->scattered_rx)
-		rxq->rx_buf_size = bufsz + ETHER_HDR_LEN +
-				   ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
-	else
-		rxq->rx_buf_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
-	/* Align to cache-line size if needed */
-	rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
+	rc = qede_calc_rx_buf_size(dev, bufsz, max_rx_pkt_len);
+	if (rc < 0) {
+		rte_free(rxq);
+		return rc;
+	}
+
+	rxq->rx_buf_size = rc;
 
 	DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 		qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
diff --git a/drivers/net/qede/qede_rxtx.h b/drivers/net/qede/qede_rxtx.h
index 9db9fed..3ab1894 100644
--- a/drivers/net/qede/qede_rxtx.h
+++ b/drivers/net/qede/qede_rxtx.h
@@ -63,9 +63,16 @@
 #define QEDE_FW_RX_ALIGN_END	(1UL << QEDE_RX_ALIGN_SHIFT)
 #define QEDE_CEIL_TO_CACHE_LINE_SIZE(n) (((n) + (QEDE_FW_RX_ALIGN_END - 1)) & \
 					~(QEDE_FW_RX_ALIGN_END - 1))
-/* Note: QEDE_LLC_SNAP_HDR_LEN is optional */
-#define QEDE_ETH_OVERHEAD	(((2 * QEDE_VLAN_TAG_SIZE)) - (ETHER_CRC_LEN) \
-				+ (QEDE_LLC_SNAP_HDR_LEN))
+#define QEDE_FLOOR_TO_CACHE_LINE_SIZE(n) RTE_ALIGN_FLOOR(n, \
+							 QEDE_FW_RX_ALIGN_END)
+
+/* Note: QEDE_LLC_SNAP_HDR_LEN is optional,
+ * +2 is for padding in front of L2 header
+ */
+#define QEDE_ETH_OVERHEAD	(((2 * QEDE_VLAN_TAG_SIZE)) \
+				 + (QEDE_LLC_SNAP_HDR_LEN) + 2)
+
+#define QEDE_MAX_ETHER_HDR_LEN	(ETHER_HDR_LEN + QEDE_ETH_OVERHEAD)
 
 #define QEDE_RSS_OFFLOAD_ALL    (ETH_RSS_IPV4			|\
 				 ETH_RSS_NONFRAG_IPV4_TCP	|\
@@ -271,6 +278,8 @@ uint16_t qede_rxtx_pkts_dummy(void *p_rxq,
 int qede_start_queues(struct rte_eth_dev *eth_dev);
 
 void qede_stop_queues(struct rte_eth_dev *eth_dev);
+int qede_calc_rx_buf_size(struct rte_eth_dev *dev, uint16_t mbufsz,
+			  uint16_t max_frame_size);
 
 /* Fastpath resource alloc/dealloc helpers */
 int qede_alloc_fp_resc(struct qede_dev *qdev);
-- 
1.7.10.3

[dpdk-stable] [PATCH 17.11 4/5] net/qede: fix Tx tunnel offload support mask

[Mody, Rasesh]

From: Shahed Shaikh <shahed.shaikh@cavium.com>

[ backported from upstream commit 49d3978d5723a3a71c348e1623cd10d489c0d4c0 ]

Tunneling offloads are represented by multi-bit values. So, feature
wise tunneling offload can only be entirely supported/unsupported
using PKT_TX_TUNNEL_MASK. Its upon PMDs to further isolate which of
the tunneling offload types are supported by respective PMD.
Using subset of bits from PKT_TX_TUNNEL_MASK to indicate supported vs
unsupported offloads can lead to undesired result.

Use PKT_TX_TUNNEL_MASK in QEDE_TX_OFFLOAD_MASK and use independent
value of supported PKT_TX_TUNNEL_* in .tx_pkt_prepare() to mark
supported tunnel offloads.

Fixes: 44346c24b790 ("net/qede: fix VXLAN tunnel Tx offload flag setting")

Suggested-by: Ferruh Yigit <ferruh.yigit@intel.com>
Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>
Reviewed-by: Rasesh Mody <rasesh.mody@cavium.com>
---
 drivers/net/qede/qede_rxtx.c |   10 ++++++++++
 drivers/net/qede/qede_rxtx.h |    3 +--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c
index 32eae81..cdb85c2 100644
--- a/drivers/net/qede/qede_rxtx.c
+++ b/drivers/net/qede/qede_rxtx.c
@@ -1764,6 +1764,16 @@ static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
 			}
 		}
 		if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
+			/* We support only limited tunnel protocols */
+			if (ol_flags & PKT_TX_TUNNEL_MASK) {
+				uint64_t temp;
+
+				temp = ol_flags & PKT_TX_TUNNEL_MASK;
+				if (temp == PKT_TX_TUNNEL_VXLAN ||
+				    temp == PKT_TX_TUNNEL_MPLSINUDP)
+					break;
+			}
+
 			rte_errno = -ENOTSUP;
 			break;
 		}
diff --git a/drivers/net/qede/qede_rxtx.h b/drivers/net/qede/qede_rxtx.h
index 3ab1894..fe80237 100644
--- a/drivers/net/qede/qede_rxtx.h
+++ b/drivers/net/qede/qede_rxtx.h
@@ -159,8 +159,7 @@
 #define QEDE_TX_OFFLOAD_MASK (QEDE_TX_CSUM_OFFLOAD_MASK | \
 			      PKT_TX_QINQ_PKT           | \
 			      PKT_TX_VLAN_PKT		| \
-			      PKT_TX_TUNNEL_VXLAN	| \
-			      PKT_TX_TUNNEL_MPLSINUDP)
+			      PKT_TX_TUNNEL_MASK)
 
 #define QEDE_TX_OFFLOAD_NOTSUP_MASK \
 	(PKT_TX_OFFLOAD_MASK ^ QEDE_TX_OFFLOAD_MASK)
-- 
1.7.10.3

[dpdk-stable] [PATCH 17.11 5/5] net/qede/base: fix to handle stag update event

[Mody, Rasesh]

[ upstream commit cb71992793940ce5b642d843e07c934a11f3c13b ]

This fix adds a ecore_mcp_update_stag() handler to handle the STAG update
events from management FW and program the STAG value.
It also clears the stag config on PF, when management FW invalidates
the stag value.

Fixes: ec94dbc57362 ("qede: add base driver")

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
---
 drivers/net/qede/base/bcm_osal.h      |    1 +
 drivers/net/qede/base/ecore_mcp.c     |   46 +++++++++++++++++++++++++++++++++
 drivers/net/qede/base/ecore_mcp_api.h |    4 +++
 drivers/net/qede/base/mcp_public.h    |    1 +
 drivers/net/qede/base/reg_addr.h      |    5 ++++
 5 files changed, 57 insertions(+)

diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h
index 52c2f0e..a5dde7a 100644
--- a/drivers/net/qede/base/bcm_osal.h
+++ b/drivers/net/qede/base/bcm_osal.h
@@ -449,6 +449,7 @@ void qede_get_mcp_proto_stats(struct ecore_dev *, enum ecore_mcp_protocol_type,
 #define OSAL_CRC8(table, pdata, nbytes, crc) 0
 #define OSAL_MFW_TLV_REQ(p_hwfn) nothing
 #define OSAL_MFW_FILL_TLV_DATA(type, buf, data) (0)
+#define OSAL_HW_INFO_CHANGE(p_hwfn, change) nothing
 #define OSAL_MFW_CMD_PREEMPT(p_hwfn) nothing
 #define OSAL_PF_VALIDATE_MODIFY_TUNN_CONFIG(p_hwfn, mask, b_update, tunn) 0
 
diff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c
index 8edd2e9..8adb7fb 100644
--- a/drivers/net/qede/base/ecore_mcp.c
+++ b/drivers/net/qede/base/ecore_mcp.c
@@ -1648,6 +1648,49 @@ static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
 		      &param);
 }
 
+static void ecore_mcp_update_stag(struct ecore_hwfn *p_hwfn,
+				  struct ecore_ptt *p_ptt)
+{
+	struct public_func shmem_info;
+	u32 resp = 0, param = 0;
+
+	ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
+				 MCP_PF_ID(p_hwfn));
+
+	p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
+						 FUNC_MF_CFG_OV_STAG_MASK;
+	p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
+	if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) {
+		if (p_hwfn->hw_info.ovlan != ECORE_MCP_VLAN_UNSET) {
+			ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE,
+				 p_hwfn->hw_info.ovlan);
+			ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 1);
+
+			/* Configure DB to add external vlan to EDPM packets */
+			ecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);
+			ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2,
+				 p_hwfn->hw_info.ovlan);
+		} else {
+			ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_EN, 0);
+			ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE, 0);
+
+			/* Configure DB to add external vlan to EDPM packets */
+			ecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 0);
+			ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_EXT_VID_BB_K2, 0);
+		}
+
+		ecore_sp_pf_update_stag(p_hwfn);
+	}
+
+	DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "ovlan  = %d hw_mode = 0x%x\n",
+		   p_hwfn->mcp_info->func_info.ovlan, p_hwfn->hw_info.hw_mode);
+	OSAL_HW_INFO_CHANGE(p_hwfn, ECORE_HW_INFO_CHANGE_OVLAN);
+
+	/* Acknowledge the MFW */
+	ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
+		      &resp, &param);
+}
+
 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn)
 {
 	/* A single notification should be sent to upper driver in CMT mode */
@@ -2033,6 +2076,9 @@ enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
 		case MFW_DRV_MSG_BW_UPDATE:
 			ecore_mcp_update_bw(p_hwfn, p_ptt);
 			break;
+		case MFW_DRV_MSG_S_TAG_UPDATE:
+			ecore_mcp_update_stag(p_hwfn, p_ptt);
+			break;
 		case MFW_DRV_MSG_FAILURE_DETECTED:
 			ecore_mcp_handle_fan_failure(p_hwfn);
 			break;
diff --git a/drivers/net/qede/base/ecore_mcp_api.h b/drivers/net/qede/base/ecore_mcp_api.h
index be3e91f..6b7a987 100644
--- a/drivers/net/qede/base/ecore_mcp_api.h
+++ b/drivers/net/qede/base/ecore_mcp_api.h
@@ -523,6 +523,10 @@ struct ecore_mfw_tlv_iscsi {
 	struct ecore_mfw_tlv_iscsi iscsi;
 };
 
+enum ecore_hw_info_change {
+	ECORE_HW_INFO_CHANGE_OVLAN,
+};
+
 /**
  * @brief - returns the link params of the hw function
  *
diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h
index b83b241..8070d28 100644
--- a/drivers/net/qede/base/mcp_public.h
+++ b/drivers/net/qede/base/mcp_public.h
@@ -1259,6 +1259,7 @@ struct public_drv_mb {
  */
 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG		0x34000000
 #define DRV_MSG_SET_RESOURCE_VALUE_MSG		0x35000000
+#define DRV_MSG_CODE_S_TAG_UPDATE_ACK		0x3b000000
 
 /*deprecated don't use*/
 #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED    0x02000000
diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h
index 8f226ad..da89ade 100644
--- a/drivers/net/qede/base/reg_addr.h
+++ b/drivers/net/qede/base/reg_addr.h
@@ -1237,3 +1237,8 @@
   #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1 << 10)
 #define PRS_REG_SEARCH_TENANT_ID 0x1f044cUL
 #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL
+
+#define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL
+#define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL
+#define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL
+#define DORQ_REG_PF_EXT_VID_BB_K2 0x1008c8UL
-- 
1.7.10.3

Re: [dpdk-stable] [PATCH 17.11 1/5] net/qede/base: fix MFW FLR flow

[Yongseok Koh]

> On Dec 18, 2018, at 4:42 PM, Mody, Rasesh <Rasesh.Mody@cavium.com> wrote:
> 
> From: Shahed Shaikh <shahed.shaikh@cavium.com>
> 
> [ backported from upstream commit 797ce8eec7c1b9e37dd9398403e9bc888cca0013 ]
> 
> Management firmware does not properly clean IGU block in PF FLR flow
> which may result in undelivered attentions for link events from
> default status block.
> Add a workaround in PMD to execute extra IGU cleanup right after PF FLR
> is done.
> 
> Fixes: 9e2f08a4ad5f ("net/qede/base: add request for PF FLR before load request")
> 
> Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>

Thanks, I was waiting for patches from you. :-)

Series applied to stable/18.11

Yongseok

> ---
> drivers/net/qede/base/ecore_dev.c  |    7 +++++++
> drivers/net/qede/base/ecore_int.c  |   32 ++++++++++++++++++++++++++++++++
> drivers/net/qede/base/ecore_int.h  |    1 +
> drivers/net/qede/base/mcp_public.h |    2 ++
> drivers/net/qede/base/reg_addr.h   |   15 +++++++++++++++
> 5 files changed, 57 insertions(+)
> 
> diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
> index 092606b..6a3046d 100644
> --- a/drivers/net/qede/base/ecore_dev.c
> +++ b/drivers/net/qede/base/ecore_dev.c
> @@ -4096,6 +4096,13 @@ void ecore_prepare_hibernate(struct ecore_dev *p_dev)
> 		rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
> 		if (rc != ECORE_SUCCESS)
> 			DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
> +
> +		/* Workaround for MFW issue where PF FLR does not cleanup
> +		 * IGU block
> +		 */
> +		if (!(p_hwfn->mcp_info->capabilities &
> +		      FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
> +			ecore_pf_flr_igu_cleanup(p_hwfn);
> 	}
> 
> 	/* Check if mdump logs/data are present and update the epoch value */
> diff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c
> index 61e36a4..b2582aa 100644
> --- a/drivers/net/qede/base/ecore_int.c
> +++ b/drivers/net/qede/base/ecore_int.c
> @@ -2679,3 +2679,35 @@ enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
> 
> 	return ECORE_SUCCESS;
> }
> +
> +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn)
> +{
> +	struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
> +	struct ecore_ptt *p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
> +							     RESERVED_PTT_DPC);
> +	int i;
> +
> +	/* Do not reorder the following cleanup sequence */
> +	/* Ack all attentions */
> +	ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff);
> +
> +	/* Clear driver attention */
> +	ecore_wr(p_hwfn,  p_dpc_ptt,
> +		((p_hwfn->rel_pf_id << 3) + MISC_REG_AEU_GENERAL_ATTN_0), 0);
> +
> +	/* Clear per-PF IGU registers to restore them as if the IGU
> +	 * was reset for this PF
> +	 */
> +	ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
> +	ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
> +	ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
> +
> +	/* Execute IGU clean up*/
> +	ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1);
> +
> +	/* Clear Stats */
> +	ecore_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED, 0);
> +
> +	for (i = 0; i < IGU_REG_PBA_STS_PF_SIZE; i++)
> +		ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0);
> +}
> diff --git a/drivers/net/qede/base/ecore_int.h b/drivers/net/qede/base/ecore_int.h
> index 563051c..ebee68b 100644
> --- a/drivers/net/qede/base/ecore_int.h
> +++ b/drivers/net/qede/base/ecore_int.h
> @@ -258,4 +258,5 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
> enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hwfn,
> 						   struct ecore_ptt *p_ptt);
> 
> +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn);
> #endif /* __ECORE_INT_H__ */
> diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h
> index 81ca663..b83b241 100644
> --- a/drivers/net/qede/base/mcp_public.h
> +++ b/drivers/net/qede/base/mcp_public.h
> @@ -1777,6 +1777,8 @@ struct public_drv_mb {
> #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ   0x00000001
> /* MFW supports EEE */
> #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002
> +/* MFW support complete IGU cleanup upon FLR */
> +#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP	0x00000080
> /* MFW supports virtual link */
> #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK       0x00010000
> 
> diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h
> index ad15d28..8f226ad 100644
> --- a/drivers/net/qede/base/reg_addr.h
> +++ b/drivers/net/qede/base/reg_addr.h
> @@ -332,6 +332,21 @@
> 	0x180820UL
> #define  IGU_REG_ATTN_MSG_ADDR_H	\
> 	0x180824UL
> +#define IGU_REG_LEADING_EDGE_LATCH \
> +	0x18082cUL
> +#define IGU_REG_TRAILING_EDGE_LATCH \
> +	0x180830UL
> +#define IGU_REG_ATTENTION_ACK_BITS \
> +	0x180838UL
> +#define IGU_REG_PBA_STS_PF \
> +	0x180d20UL
> +#define IGU_REG_PF_FUNCTIONAL_CLEANUP \
> +	0x181210UL
> +#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \
> +	0x18042cUL
> +#define IGU_REG_PBA_STS_PF_SIZE 5
> +#define IGU_REG_PBA_STS_PF \
> +	0x180d20UL
> #define  MISC_REG_AEU_GENERAL_ATTN_0 \
> 	0x008400UL
> #define  CAU_REG_SB_ADDR_MEMORY \
> -- 
> 1.7.10.3
> 

Re: [dpdk-stable] [PATCH 17.11 1/5] net/qede/base: fix MFW FLR flow

[Rasesh Mody]

>From: Yongseok Koh <yskoh@mellanox.com>
>Sent: Wednesday, December 19, 2018 12:09 PM
>
>> On Dec 18, 2018, at 4:42 PM, Mody, Rasesh <Rasesh.Mody@cavium.com>
>wrote:
>>
>> From: Shahed Shaikh <shahed.shaikh@cavium.com>
>>
>> [ backported from upstream commit
>> 797ce8eec7c1b9e37dd9398403e9bc888cca0013 ]
>>
>> Management firmware does not properly clean IGU block in PF FLR flow
>> which may result in undelivered attentions for link events from
>> default status block.
>> Add a workaround in PMD to execute extra IGU cleanup right after PF
>> FLR is done.
>>
>> Fixes: 9e2f08a4ad5f ("net/qede/base: add request for PF FLR before
>> load request")
>>
>> Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>
>
>Thanks, I was waiting for patches from you. :-)
>
>Series applied to stable/18.11

Thanks, you mean stable/17.11, right?

-Rasesh
>
>Yongseok
>
>> ---
>> drivers/net/qede/base/ecore_dev.c  |    7 +++++++
>> drivers/net/qede/base/ecore_int.c  |   32
>++++++++++++++++++++++++++++++++
>> drivers/net/qede/base/ecore_int.h  |    1 +
>> drivers/net/qede/base/mcp_public.h |    2 ++
>> drivers/net/qede/base/reg_addr.h   |   15 +++++++++++++++
>> 5 files changed, 57 insertions(+)
>>
>> diff --git a/drivers/net/qede/base/ecore_dev.c
>> b/drivers/net/qede/base/ecore_dev.c
>> index 092606b..6a3046d 100644
>> --- a/drivers/net/qede/base/ecore_dev.c
>> +++ b/drivers/net/qede/base/ecore_dev.c
>> @@ -4096,6 +4096,13 @@ void ecore_prepare_hibernate(struct ecore_dev
>*p_dev)
>>               rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
>>               if (rc != ECORE_SUCCESS)
>>                       DP_NOTICE(p_hwfn, false, "Failed to initiate PF
>> FLR\n");
>> +
>> +             /* Workaround for MFW issue where PF FLR does not cleanup
>> +              * IGU block
>> +              */
>> +             if (!(p_hwfn->mcp_info->capabilities &
>> +                   FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
>> +                     ecore_pf_flr_igu_cleanup(p_hwfn);
>>       }
>>
>>       /* Check if mdump logs/data are present and update the epoch
>> value */ diff --git a/drivers/net/qede/base/ecore_int.c
>> b/drivers/net/qede/base/ecore_int.c
>> index 61e36a4..b2582aa 100644
>> --- a/drivers/net/qede/base/ecore_int.c
>> +++ b/drivers/net/qede/base/ecore_int.c
>> @@ -2679,3 +2679,35 @@ enum _ecore_status_t
>> ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
>>
>>       return ECORE_SUCCESS;
>> }
>> +
>> +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn) {
>> +     struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
>> +     struct ecore_ptt *p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
>> +                                                          RESERVED_PTT_DPC);
>> +     int i;
>> +
>> +     /* Do not reorder the following cleanup sequence */
>> +     /* Ack all attentions */
>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff);
>> +
>> +     /* Clear driver attention */
>> +     ecore_wr(p_hwfn,  p_dpc_ptt,
>> +             ((p_hwfn->rel_pf_id << 3) +
>> + MISC_REG_AEU_GENERAL_ATTN_0), 0);
>> +
>> +     /* Clear per-PF IGU registers to restore them as if the IGU
>> +      * was reset for this PF
>> +      */
>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
>> +
>> +     /* Execute IGU clean up*/
>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1);
>> +
>> +     /* Clear Stats */
>> +     ecore_wr(p_hwfn, p_ptt,
>IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED,
>> + 0);
>> +
>> +     for (i = 0; i < IGU_REG_PBA_STS_PF_SIZE; i++)
>> +             ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0);
>> +}
>> diff --git a/drivers/net/qede/base/ecore_int.h
>> b/drivers/net/qede/base/ecore_int.h
>> index 563051c..ebee68b 100644
>> --- a/drivers/net/qede/base/ecore_int.h
>> +++ b/drivers/net/qede/base/ecore_int.h
>> @@ -258,4 +258,5 @@ enum _ecore_status_t
>> ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn, enum
>_ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn
>*p_hwfn,
>>                                                  struct ecore_ptt
>> *p_ptt);
>>
>> +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn);
>> #endif /* __ECORE_INT_H__ */
>> diff --git a/drivers/net/qede/base/mcp_public.h
>> b/drivers/net/qede/base/mcp_public.h
>> index 81ca663..b83b241 100644
>> --- a/drivers/net/qede/base/mcp_public.h
>> +++ b/drivers/net/qede/base/mcp_public.h
>> @@ -1777,6 +1777,8 @@ struct public_drv_mb {
>> #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ   0x00000001
>> /* MFW supports EEE */
>> #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002
>> +/* MFW support complete IGU cleanup upon FLR */
>> +#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP
>0x00000080
>> /* MFW supports virtual link */
>> #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK       0x00010000
>>
>> diff --git a/drivers/net/qede/base/reg_addr.h
>> b/drivers/net/qede/base/reg_addr.h
>> index ad15d28..8f226ad 100644
>> --- a/drivers/net/qede/base/reg_addr.h
>> +++ b/drivers/net/qede/base/reg_addr.h
>> @@ -332,6 +332,21 @@
>>       0x180820UL
>> #define  IGU_REG_ATTN_MSG_ADDR_H      \
>>       0x180824UL
>> +#define IGU_REG_LEADING_EDGE_LATCH \
>> +     0x18082cUL
>> +#define IGU_REG_TRAILING_EDGE_LATCH \
>> +     0x180830UL
>> +#define IGU_REG_ATTENTION_ACK_BITS \
>> +     0x180838UL
>> +#define IGU_REG_PBA_STS_PF \
>> +     0x180d20UL
>> +#define IGU_REG_PF_FUNCTIONAL_CLEANUP \
>> +     0x181210UL
>> +#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \
>> +     0x18042cUL
>> +#define IGU_REG_PBA_STS_PF_SIZE 5
>> +#define IGU_REG_PBA_STS_PF \
>> +     0x180d20UL
>> #define  MISC_REG_AEU_GENERAL_ATTN_0 \
>>       0x008400UL
>> #define  CAU_REG_SB_ADDR_MEMORY \
>> --
>> 1.7.10.3
>>

Re: [dpdk-stable] [PATCH 17.11 1/5] net/qede/base: fix MFW FLR flow

[Yongseok Koh]

> On Dec 19, 2018, at 2:18 PM, Rasesh Mody <rmody@marvell.com> wrote:
> 
>> From: Yongseok Koh <yskoh@mellanox.com>
>> Sent: Wednesday, December 19, 2018 12:09 PM
>> 
>>> On Dec 18, 2018, at 4:42 PM, Mody, Rasesh <Rasesh.Mody@cavium.com>
>> wrote:
>>> 
>>> From: Shahed Shaikh <shahed.shaikh@cavium.com>
>>> 
>>> [ backported from upstream commit
>>> 797ce8eec7c1b9e37dd9398403e9bc888cca0013 ]
>>> 
>>> Management firmware does not properly clean IGU block in PF FLR flow
>>> which may result in undelivered attentions for link events from
>>> default status block.
>>> Add a workaround in PMD to execute extra IGU cleanup right after PF
>>> FLR is done.
>>> 
>>> Fixes: 9e2f08a4ad5f ("net/qede/base: add request for PF FLR before
>>> load request")
>>> 
>>> Signed-off-by: Shahed Shaikh <shahed.shaikh@cavium.com>
>> 
>> Thanks, I was waiting for patches from you. :-)
>> 
>> Series applied to stable/18.11
> 
> Thanks, you mean stable/17.11, right?

Right, that was a typo. :-)

Yongseok

>> 
>>> ---
>>> drivers/net/qede/base/ecore_dev.c  |    7 +++++++
>>> drivers/net/qede/base/ecore_int.c  |   32
>> ++++++++++++++++++++++++++++++++
>>> drivers/net/qede/base/ecore_int.h  |    1 +
>>> drivers/net/qede/base/mcp_public.h |    2 ++
>>> drivers/net/qede/base/reg_addr.h   |   15 +++++++++++++++
>>> 5 files changed, 57 insertions(+)
>>> 
>>> diff --git a/drivers/net/qede/base/ecore_dev.c
>>> b/drivers/net/qede/base/ecore_dev.c
>>> index 092606b..6a3046d 100644
>>> --- a/drivers/net/qede/base/ecore_dev.c
>>> +++ b/drivers/net/qede/base/ecore_dev.c
>>> @@ -4096,6 +4096,13 @@ void ecore_prepare_hibernate(struct ecore_dev
>> *p_dev)
>>>              rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
>>>              if (rc != ECORE_SUCCESS)
>>>                      DP_NOTICE(p_hwfn, false, "Failed to initiate PF
>>> FLR\n");
>>> +
>>> +             /* Workaround for MFW issue where PF FLR does not cleanup
>>> +              * IGU block
>>> +              */
>>> +             if (!(p_hwfn->mcp_info->capabilities &
>>> +                   FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP))
>>> +                     ecore_pf_flr_igu_cleanup(p_hwfn);
>>>      }
>>> 
>>>      /* Check if mdump logs/data are present and update the epoch
>>> value */ diff --git a/drivers/net/qede/base/ecore_int.c
>>> b/drivers/net/qede/base/ecore_int.c
>>> index 61e36a4..b2582aa 100644
>>> --- a/drivers/net/qede/base/ecore_int.c
>>> +++ b/drivers/net/qede/base/ecore_int.c
>>> @@ -2679,3 +2679,35 @@ enum _ecore_status_t
>>> ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
>>> 
>>>      return ECORE_SUCCESS;
>>> }
>>> +
>>> +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn) {
>>> +     struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
>>> +     struct ecore_ptt *p_dpc_ptt = ecore_get_reserved_ptt(p_hwfn,
>>> +                                                          RESERVED_PTT_DPC);
>>> +     int i;
>>> +
>>> +     /* Do not reorder the following cleanup sequence */
>>> +     /* Ack all attentions */
>>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff);
>>> +
>>> +     /* Clear driver attention */
>>> +     ecore_wr(p_hwfn,  p_dpc_ptt,
>>> +             ((p_hwfn->rel_pf_id << 3) +
>>> + MISC_REG_AEU_GENERAL_ATTN_0), 0);
>>> +
>>> +     /* Clear per-PF IGU registers to restore them as if the IGU
>>> +      * was reset for this PF
>>> +      */
>>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
>>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
>>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
>>> +
>>> +     /* Execute IGU clean up*/
>>> +     ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1);
>>> +
>>> +     /* Clear Stats */
>>> +     ecore_wr(p_hwfn, p_ptt,
>> IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED,
>>> + 0);
>>> +
>>> +     for (i = 0; i < IGU_REG_PBA_STS_PF_SIZE; i++)
>>> +             ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0);
>>> +}
>>> diff --git a/drivers/net/qede/base/ecore_int.h
>>> b/drivers/net/qede/base/ecore_int.h
>>> index 563051c..ebee68b 100644
>>> --- a/drivers/net/qede/base/ecore_int.h
>>> +++ b/drivers/net/qede/base/ecore_int.h
>>> @@ -258,4 +258,5 @@ enum _ecore_status_t
>>> ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn, enum
>> _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn
>> *p_hwfn,
>>>                                                 struct ecore_ptt
>>> *p_ptt);
>>> 
>>> +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn);
>>> #endif /* __ECORE_INT_H__ */
>>> diff --git a/drivers/net/qede/base/mcp_public.h
>>> b/drivers/net/qede/base/mcp_public.h
>>> index 81ca663..b83b241 100644
>>> --- a/drivers/net/qede/base/mcp_public.h
>>> +++ b/drivers/net/qede/base/mcp_public.h
>>> @@ -1777,6 +1777,8 @@ struct public_drv_mb {
>>> #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ   0x00000001
>>> /* MFW supports EEE */
>>> #define FW_MB_PARAM_FEATURE_SUPPORT_EEE         0x00000002
>>> +/* MFW support complete IGU cleanup upon FLR */
>>> +#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP
>> 0x00000080
>>> /* MFW supports virtual link */
>>> #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK       0x00010000
>>> 
>>> diff --git a/drivers/net/qede/base/reg_addr.h
>>> b/drivers/net/qede/base/reg_addr.h
>>> index ad15d28..8f226ad 100644
>>> --- a/drivers/net/qede/base/reg_addr.h
>>> +++ b/drivers/net/qede/base/reg_addr.h
>>> @@ -332,6 +332,21 @@
>>>      0x180820UL
>>> #define  IGU_REG_ATTN_MSG_ADDR_H      \
>>>      0x180824UL
>>> +#define IGU_REG_LEADING_EDGE_LATCH \
>>> +     0x18082cUL
>>> +#define IGU_REG_TRAILING_EDGE_LATCH \
>>> +     0x180830UL
>>> +#define IGU_REG_ATTENTION_ACK_BITS \
>>> +     0x180838UL
>>> +#define IGU_REG_PBA_STS_PF \
>>> +     0x180d20UL
>>> +#define IGU_REG_PF_FUNCTIONAL_CLEANUP \
>>> +     0x181210UL
>>> +#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \
>>> +     0x18042cUL
>>> +#define IGU_REG_PBA_STS_PF_SIZE 5
>>> +#define IGU_REG_PBA_STS_PF \
>>> +     0x180d20UL
>>> #define  MISC_REG_AEU_GENERAL_ATTN_0 \
>>>      0x008400UL
>>> #define  CAU_REG_SB_ADDR_MEMORY \
>>> --
>>> 1.7.10.3