From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
To: dev@dpdk.org
Cc: rasland@nvidia.com, matan@nvidia.com, stable@dpdk.org
Subject: [dpdk-stable] [PATCH 3/4] vdpa/mlx5: fix UAR allocation
Date: Tue, 10 Nov 2020 16:04:18 +0000 [thread overview]
Message-ID: <1605024259-18318-3-git-send-email-viacheslavo@nvidia.com> (raw)
In-Reply-To: <1605024259-18318-1-git-send-email-viacheslavo@nvidia.com>
This patch provides the UAR allocation workaround for the
hosts where UAR allocation with Write-Combining memory
mapping type fails.
Fixes: 8395927cdfaf ("vdpa/mlx5: prepare HW queues")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/vdpa/mlx5/mlx5_vdpa_event.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
index 010543c..3aeaeb8 100644
--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c
+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
@@ -77,7 +77,12 @@
DRV_LOG(ERR, "Failed to change event channel FD.");
goto error;
}
- priv->uar = mlx5_glue->devx_alloc_uar(priv->ctx, 0);
+ /*
+ * This PMD always claims the write memory barrier on UAR
+ * registers writings, it is safe to allocate UAR with any
+ * memory mapping type.
+ */
+ priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
if (!priv->uar) {
rte_errno = errno;
DRV_LOG(ERR, "Failed to allocate UAR.");
--
1.8.3.1
next prev parent reply other threads:[~2020-11-10 16:04 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-10 16:04 [dpdk-stable] [PATCH 1/4] common/mlx5: share UAR allocation routine Viacheslav Ovsiienko
2020-11-10 16:04 ` [dpdk-stable] [PATCH 2/4] regex/mlx5: fix UAR allocation Viacheslav Ovsiienko
2020-11-10 16:04 ` Viacheslav Ovsiienko [this message]
2020-11-14 8:36 ` [dpdk-stable] [PATCH 1/4] common/mlx5: share UAR allocation routine Thomas Monjalon
2020-11-14 10:01 ` Thomas Monjalon
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