From: Bing Zhao <bingz@nvidia.com>
To: viacheslavo@nvidia.com, matan@nvidia.com
Cc: dev@dpdk.org, orika@nvidia.com, rasland@nvidia.com, stable@dpdk.org
Subject: [dpdk-stable] [PATCH] net/mlx5: fix eCPRI item value with mask
Date: Thu, 19 Nov 2020 10:41:32 +0800 [thread overview]
Message-ID: <1605753692-311910-1-git-send-email-bingz@nvidia.com> (raw)
When creating a flow with eCPRI item, the mask and the value are both
needed in order to build the matching criteria.
In the current implementation, the unused value bits clear operation
was missed when filling the mask and value fields. For the value, the
bits not required were not masked with the mask provided. Indeed,
this action is not mandatory. But when creating a flow in the root
table, the kernel driver got involved and a check would prevent this
flow from being created. The same flow could be created successfully
with the userspace rdma-core on the non-root tables.
An AND operation needs to be added to clear the unused bits in the
value when building the matching criteria. Then the same flow can be
created successfully no matter with kernel driver or with rdma-core.
Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header")
Cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/net/mlx5/mlx5_flow_dv.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 1f0a2ab..c7840da 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7875,7 +7875,7 @@ flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
prog_sample_field_value_0);
/* Already big endian (network order) in the header. */
*(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
- *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
+ *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
/* Sample#0, used for matching type, offset 0. */
MLX5_SET(fte_match_set_misc4, misc4_m,
prog_sample_field_id_0, samples[0]);
@@ -7897,7 +7897,8 @@ flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
prog_sample_field_value_1);
*(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
- *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
+ *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
+ ecpri_m->hdr.dummy[0];
/* Sample#1, to match message body, offset 4. */
MLX5_SET(fte_match_set_misc4, misc4_m,
prog_sample_field_id_1, samples[1]);
--
2.5.5
next reply other threads:[~2020-11-19 2:41 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 2:41 Bing Zhao [this message]
2020-11-19 10:52 ` Raslan Darawsheh
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