From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7DA6DA0549 for ; Mon, 8 Feb 2021 04:04:14 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C61321606BF; Mon, 8 Feb 2021 04:04:13 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 780ED40147 for ; Mon, 8 Feb 2021 04:04:12 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from suanmingm@nvidia.com) with SMTP; 8 Feb 2021 05:04:08 +0200 Received: from nvidia.com (mtbc-r640-04.mtbc.labs.mlnx [10.75.70.9]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 11834525016774; Mon, 8 Feb 2021 05:04:07 +0200 From: Suanming Mou To: christian.ehrhardt@canonical.com Cc: viacheslavo@nvidia.com, stable@dpdk.org Date: Mon, 8 Feb 2021 11:04:00 +0800 Message-Id: <1612753441-328529-2-git-send-email-suanmingm@nvidia.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1612753441-328529-1-git-send-email-suanmingm@nvidia.com> References: <1612753441-328529-1-git-send-email-suanmingm@nvidia.com> Subject: [dpdk-stable] [PATCH 19.11 1/2] net/mlx5: fix crash on secondary process port close X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" [ upstream commit 84a22cbcc467a02772dd24156773940331994c84 ] When secondary process starts, in rte_eth_dev_attach_secondary() function, the secondary process port device data in struct rte_eth_dev will be initialized to be shared with primary process port. When failsafe sub-port hot-plug happens, both primary and secondary process will release the sub-port, and primary process will clear the sub-port device data in fs_dev_remove() deactivate stage first before request secondary process to release the sub-port. In this case, the secondary process will not be able to get the priv memory pointer from the shared device data memory anymore, since the device data memory has been cleared. Since what secondary process needs in port detach is the UAR table size to unmap the UAR addresses. It used Tx queue number as size of UAR table in priv. In fact the uar_table_sz in struct mlx5_proc_priv means the size of UAR register table - the number of UAR records. However, the code set this field incorrectly to the size of mlx5_proc_priv structure. This commit fixes UAR table size to match with relevant Tx queue number, uses the UAR table size directly to avoid the secondary process to access the priv pointer in the shared device data memory when unmapping the UAR address. Fixes: 120dc4a7dcd3 ("net/mlx5: remove device register remap") Cc: stable@dpdk.org Signed-off-by: Suanming Mou Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.c | 4 ++-- drivers/net/mlx5/mlx5_txq.c | 21 +++++++++++++-------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 4307005..ac47452 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1251,13 +1251,13 @@ struct mlx5_flow_id_pool * */ ppriv_size = sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); - ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size, + ppriv = rte_zmalloc_socket("mlx5_proc_priv", ppriv_size, RTE_CACHE_LINE_SIZE, dev->device->numa_node); if (!ppriv) { rte_errno = ENOMEM; return -rte_errno; } - ppriv->uar_table_sz = ppriv_size; + ppriv->uar_table_sz = priv->txqs_n; dev->process_private = ppriv; return 0; } diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index 36aa9b5..0fb3ceb 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -433,18 +433,23 @@ void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev) { - struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_txq_data *txq; - struct mlx5_txq_ctrl *txq_ctrl; + struct mlx5_proc_priv *ppriv = (struct mlx5_proc_priv *) + dev->process_private; + const size_t page_size = sysconf(_SC_PAGESIZE); + void *addr; unsigned int i; + if (page_size == (size_t)-1) { + DRV_LOG(ERR, "Failed to get mem page size"); + return; + } assert(rte_eal_process_type() == RTE_PROC_SECONDARY); - for (i = 0; i != priv->txqs_n; ++i) { - if (!(*priv->txqs)[i]) + for (i = 0; i != ppriv->uar_table_sz; ++i) { + if (!ppriv->uar_table[i]) continue; - txq = (*priv->txqs)[i]; - txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); - txq_uar_uninit_secondary(txq_ctrl); + addr = ppriv->uar_table[i]; + munmap(RTE_PTR_ALIGN_FLOOR(addr, page_size), page_size); + } } -- 1.8.3.1