From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5490BA0C4D for ; Thu, 17 Jun 2021 08:55:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1F77B40150; Thu, 17 Jun 2021 08:55:04 +0200 (CEST) Received: from out0-141.mail.aliyun.com (out0-141.mail.aliyun.com [140.205.0.141]) by mails.dpdk.org (Postfix) with ESMTP id B1CDA40150 for ; Thu, 17 Jun 2021 08:55:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alibaba-inc.com; s=default; t=1623912900; h=From:To:Subject:Date:Message-Id; bh=ipWq5NscfP5PhzycLTal9poUXitkO43/wkISRN8GUx4=; b=nGvTuFxH/eJpQkOefZbP5yZiRV1+DH+jpUVGnC3ls3uvUgAdxawUVoROyflUzAhhWoNAru0jjMyymIaCE07zNR2x0MO/UlvTVkjwKIH5NEJQcGG0O478TRdXF297B1xapSHY26si6VUoyHiSmIJ8qdUxuPvFSM7CrN3q0TWPGxk= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R161e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018047187; MF=huawei.xhw@alibaba-inc.com; NM=1; PH=DS; RN=7; SR=0; TI=SMTPD_---.KTc.Vvu_1623912895; Received: from h33o11252.sqa.nu8.tbsite.net(mailfrom:huawei.xhw@alibaba-inc.com fp:SMTPD_---.KTc.Vvu_1623912895) by smtp.aliyun-inc.com(127.0.0.1); Thu, 17 Jun 2021 14:54:59 +0800 From: "=?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?=" To: stable@dpdk.org Cc: , , , , , "=?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?=" Date: Thu, 17 Jun 2021 14:54:50 +0800 Message-Id: <1623912892-108014-1-git-send-email-huawei.xhw@alibaba-inc.com> X-Mailer: git-send-email 1.8.3.1 Subject: [dpdk-stable] [PATCH 20.11 0/2] support both PIO and MMIO BAR for legacy virito device X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" virtio PMD assumes legacy device only supports PIO(port-mapped) BAR resource. This is wrong. As we need to create lots of devices, adn PIO resource on x86 is very limited, we expose MMIO(memory-mapped I/O) BAR. Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and for all other pci devices. This patchset handles different type of BAR in the similar way. In previous implementation, under igb_uio driver we get PIO address from igb_uio sysfs entry; with uio_pci_generic, we get PIO address from /proc/ioports for x86, and for other ARCHs, we get PIO address from standard PCI sysfs entry. For PIO/MMIO RW, there is different path for different drivers and arch. All of the above is too much twisted. This patchset unifies the way to get both PIO and MMIO address for different driver and ARCHs, all from standard resource attr under pci sysfs. This is most generic. We distinguish PIO and MMIO by their address range like how kernel does. It is ugly but works. huawei xie (2): bus/pci: use PCI standard sysfs entry to get PIO address bus/pci: support MMIO in PCI ioport accessors drivers/bus/pci/linux/pci.c | 81 --------------- drivers/bus/pci/linux/pci_uio.c | 214 ++++++++++++++++++++++++++++------------ 2 files changed, 150 insertions(+), 145 deletions(-) -- 1.8.3.1