From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by dpdk.org (Postfix) with ESMTP id CE03A493D; Mon, 5 Nov 2018 14:17:32 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 589EE22A63; Mon, 5 Nov 2018 08:17:31 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Mon, 05 Nov 2018 08:17:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=mesmtp; bh=vv9+/F/COKD5lpdAXEWImpfK9sgbSQreEXeEK3Y0viU=; b=sWKPpuZKFA6W dCWX8jJEcuWAjeG6TFFEerXP/l7oxqQzFzKYgi8IIuFp7VS4yo2P7swgYekKh7wz mJAsuHnQ995IHQ90NjqjzibzoaSQ9+gw7cq/r1BYjg5IViaYBn0o9jVjkoMKe9nq QS59sAEu/y5arFW4O/JwEJxWHYHYL/U= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=vv9+/F/COKD5lpdAXEWImpfK9sgbSQreEXeEK3Y0v iU=; b=qfr7qPuBBltcI4I/y+zyOi1gPdF7tr0Wfk8iqJ/lA25LxcRgXc8mCKZZW pSDkMhSlrvQR6955VFxIpjbiJzC5q1B6b8J6y7u3GwXHKUA8t7Rfmf0q3trIdGMO +CcyW8FE3EWZmWZcwd9PcT18lfXex6jwtDmNJ8zO6NHk/ePxFAZzXZ2fi0hGEvS6 TxBszwkNPqYthSITBqi4p0QfR2htquJwyEkbCeb2ujsTy0hxUP/tHeH8AWOxlFUJ IYejyUjdt7ZOEOniDqZ48vxUeir0YHFW3pzopneefDb/+9RwdZeFlISptMhzJ2ss oEKUwhhOGKUyh293fazcp2q87N5Vw== X-ME-Sender: X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 88B0EE49C8; Mon, 5 Nov 2018 08:17:28 -0500 (EST) From: Thomas Monjalon To: Honnappa Nagarahalli Cc: stable@dpdk.org, "Gavin Hu (Arm Technology China)" , Bruce Richardson , "dev@dpdk.org" , "stephen@networkplumber.org" , "olivier.matz@6wind.com" , "chaozhu@linux.vnet.ibm.com" , "konstantin.ananyev@intel.com" , "jerin.jacob@caviumnetworks.com" , nd , hemant.agrawal@nxp.com, shreyansh.jain@nxp.com Date: Mon, 05 Nov 2018 14:17:27 +0100 Message-ID: <1825633.NNxUzH26Cz@xps> In-Reply-To: References: <1541066031-29125-1-git-send-email-gavin.hu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-stable] [PATCH v5 2/2] ring: move the atomic load of head above the loop X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Nov 2018 13:17:33 -0000 03/11/2018 10:34, Honnappa Nagarahalli: > > > > --- > > > > doc/guides/rel_notes/release_18_11.rst | 7 +++++++ > > > > lib/librte_ring/rte_ring_c11_mem.h | 10 ++++------ > > > > 2 files changed, 11 insertions(+), 6 deletions(-) > > > > > > > > diff --git a/doc/guides/rel_notes/release_18_11.rst > > > > b/doc/guides/rel_notes/release_18_11.rst > > > > index 376128f..b68afab 100644 > > > > --- a/doc/guides/rel_notes/release_18_11.rst > > > > +++ b/doc/guides/rel_notes/release_18_11.rst > > > > @@ -69,6 +69,13 @@ New Features > > > > checked out against that dma mask and rejected if out of range. > > > > If more > > > than > > > > one device has addressing limitations, the dma mask is the more > > > restricted one. > > > > > > > > +* **Updated the ring library with C11 memory model.** > > > > + > > > > + Updated the ring library with C11 memory model, in our tests the > > > > + changes decreased latency by 27~29% and 3~15% for MPMC and SPSC > > > cases respectively. > > > > + The real improvements may vary with the number of contending > > > > + lcores and the size of ring. > > > > + > > > Is this a little misleading, and will users expect massive performance > > > improvements generally? The C11 model seems to be used only on some, > > > but not all, arm platforms, and then only with "make" builds. > > > > > > config/arm/meson.build: ['RTE_USE_C11_MEM_MODEL', false]] > This is an error. There is already an agreement that on Arm based platforms, C11 memory model would be used by default. Specific platforms can override it if required. > Would this be ab acceptable change for RC2 or RC3? If NXP and Cavium agrees, I think it can go in RC2. For RC3, not sure.