From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg0-f42.google.com (mail-pg0-f42.google.com [74.125.83.42]) by dpdk.org (Postfix) with ESMTP id 63D4F7CC7 for ; Fri, 18 Aug 2017 12:04:56 +0200 (CEST) Received: by mail-pg0-f42.google.com with SMTP id y129so61450280pgy.4 for ; Fri, 18 Aug 2017 03:04:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fridaylinux-org.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=w2xsrZyEc4qlM8yMNlpXtImvairKZoVmg0B8UTpy9uo=; b=UYas+iY3DeTrJKeHjF5vWQBJeoQT5FMyBoTpnInr77/Py/TxPwKUABPamwviOaA2TA yMmWO71s81CNoSqgulHpf6KYt9aozKLYE/+pPNvQnFAbFvLvOSju6Uv2e+9AZSsi/1pz RwcXLrky8U5JMYG9zq6biwykKmZp8fckUfRNMjOnL1vSY9NPeaPWzMZuPhh8cF7+dUkT Ha6bSz6E1UGIDecwQJzxoweH+dmlTP0r8rnSr32pljt7Ftkhm9+37XkeDj0Kb9sRYfle aafRuoDbTR50s/2DB3/4eYc6JXy6CuoK434PBvSbJp7qMn2vhDfwLyZv1SeH5eCo0DoA aK/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=w2xsrZyEc4qlM8yMNlpXtImvairKZoVmg0B8UTpy9uo=; b=GeFTG1fwxVdlYDtkHyNsE6rQxRDET+/YBGqlcjonwzNlut5pUqalUV2yTEEUxUFtHx xTlcWNt2KFCxD37Ok4UWTClTQrhxVAZNT9ROcffjwHBVMahhXPBj/N7l4Op8yVx6iQqU 8zdx2zrOwavhcVmIZzePpJ8Bfi4eAVEtGi/AW7NwHcxBjjPkQFlVVQNG46iOjcL/b8jA +18gU7pRGHUJ7XdGYVOz87EdTjMQC6RyRcEhMdUyle8Xqgc0ETBFhCvHCSG/1YddAdwD CKwXxRPrgGsQkx+RXNuzmH1fY+EfIqZOEBth8myuJI5JvqeXz39B+JEsHhDfH5MoeKVU 322Q== X-Gm-Message-State: AHYfb5h+NkRpJWn09aEg3yNxl5rV/REkgkbfNENiaXzMhWL8omyzJ7fw Q39UuwWHhKKOhvmgaMI0NA== X-Received: by 10.98.178.68 with SMTP id x65mr8310506pfe.170.1503050695469; Fri, 18 Aug 2017 03:04:55 -0700 (PDT) Received: from yliu-home ([45.63.61.64]) by smtp.gmail.com with ESMTPSA id q21sm11668637pfj.126.2017.08.18.03.04.52 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Aug 2017 03:04:54 -0700 (PDT) Date: Fri, 18 Aug 2017 18:04:48 +0800 From: Yuanhan Liu To: Jeff Guo Cc: beilei.xing@intel.com, jingjing.wu@intel.com, stable@dpdk.org Message-ID: <20170818100448.GL9612@yliu-home> References: <1503021828-2545-1-git-send-email-jia.guo@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1503021828-2545-1-git-send-email-jia.guo@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [dpdk-stable] [PATCH] net/i40e: fix link down and negotiation X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 18 Aug 2017 10:04:56 -0000 On Fri, Aug 18, 2017 at 10:03:48AM +0800, Jeff Guo wrote: > [ backported from upstream commit 1bb8f661168d942927cb65e355ec64d4ab195281 ] Thanks for the backport, but it still does't apply to 16.11 branch cleanly. FYI, you should do the backport on top of branch 16.11 of stable tree: http://dpdk.org/browse/dpdk-stable/ --yliu --- diff --cc drivers/net/i40e/i40e_ethdev.c index f65ddc7,fa0518e..0000000 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@@ -1627,10 -1850,18 +1635,24 @@@ i40e_phy_conf_link(struct i40e_hw *hw phy_conf.abilities = abilities; + + + /* To enable link, phy_type mask needs to include each type */ + for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++) + phy_type_mask |= 1 << cnt; + /* use get_phy_abilities_resp value for the rest */ ++<<<<<<< 09ae3d0c48885d20ab255922c1ca4769a32c2a12 + phy_conf.phy_type = phy_ab.phy_type; + phy_conf.phy_type_ext = phy_ab.phy_type_ext; + phy_conf.fec_config = phy_ab.mod_type_ext; ++======= + phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0; + phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR | + I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR | + I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0; + phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info; ++>>>>>>> net/i40e: fix link down and negotiation phy_conf.eee_capability = phy_ab.eee_capability; phy_conf.eeer = phy_ab.eeer_val; phy_conf.low_power_ctrl = phy_ab.d3_lpan; > > Enable the functions set link down and set link up in i40e by check > phy_type, and fix the issue of auto negotiation failed in XXV710 when > bind kernel driver after unbind from DPDK driver by modify the speed > setting distinguish from set link up and down. With this fix, if unbind > DPDK to bind kernel driver, no need to set auto negotiation and ifconfig > up anymore, remove the part from doc. > > Fixes: ca7e599d4506 ("net/i40e: fix link management") > Fixes: 2f1e22817420 ("i40e: skip link control as firmware workaround") > Fixes: 6e145fcc754b ("i40e: support autoneg or force link speed") > > Signed-off-by: Jeff Guo > Acked-by: Jingjing Wu > --- > drivers/net/i40e/i40e_ethdev.c | 34 ++++++++++++++++++++++------------ > 1 file changed, 22 insertions(+), 12 deletions(-) > > diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c > index 4c49673..fa0518e 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -1806,11 +1806,15 @@ i40e_parse_link_speeds(uint16_t link_speeds) > static int > i40e_phy_conf_link(struct i40e_hw *hw, > uint8_t abilities, > - uint8_t force_speed) > + uint8_t force_speed, > + bool is_up) > { > enum i40e_status_code status; > struct i40e_aq_get_phy_abilities_resp phy_ab; > struct i40e_aq_set_phy_config phy_conf; > + enum i40e_aq_phy_type cnt; > + uint32_t phy_type_mask = 0; > + > const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX | > I40E_AQ_PHY_FLAG_PAUSE_RX | > I40E_AQ_PHY_FLAG_PAUSE_RX | > @@ -1828,6 +1832,10 @@ i40e_phy_conf_link(struct i40e_hw *hw, > if (status) > return ret; > > + /* If link already up, no need to set up again */ > + if (is_up && phy_ab.phy_type != 0) > + return I40E_SUCCESS; > + > memset(&phy_conf, 0, sizeof(phy_conf)); > > /* bits 0-2 use the values from get_phy_abilities_resp */ > @@ -1838,13 +1846,21 @@ i40e_phy_conf_link(struct i40e_hw *hw, > if (abilities & I40E_AQ_PHY_AN_ENABLED) > phy_conf.link_speed = advt; > else > - phy_conf.link_speed = force_speed; > + phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed; > > phy_conf.abilities = abilities; > > + > + > + /* To enable link, phy_type mask needs to include each type */ > + for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++) > + phy_type_mask |= 1 << cnt; > + > /* use get_phy_abilities_resp value for the rest */ > - phy_conf.phy_type = phy_ab.phy_type; > - phy_conf.phy_type_ext = phy_ab.phy_type_ext; > + phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0; > + phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR | > + I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR | > + I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0; > phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info; > phy_conf.eee_capability = phy_ab.eee_capability; > phy_conf.eeer = phy_ab.eeer_val; > @@ -1876,13 +1892,7 @@ i40e_apply_link_speed(struct rte_eth_dev *dev) > abilities |= I40E_AQ_PHY_AN_ENABLED; > abilities |= I40E_AQ_PHY_LINK_ENABLED; > > - /* Skip changing speed on 40G interfaces, FW does not support */ > - if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) { > - speed = I40E_LINK_SPEED_UNKNOWN; > - abilities |= I40E_AQ_PHY_AN_ENABLED; > - } > - > - return i40e_phy_conf_link(hw, abilities, speed); > + return i40e_phy_conf_link(hw, abilities, speed, true); > } > > static int > @@ -2225,7 +2235,7 @@ i40e_dev_set_link_down(struct rte_eth_dev *dev) > struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); > > abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK; > - return i40e_phy_conf_link(hw, abilities, speed); > + return i40e_phy_conf_link(hw, abilities, speed, false); > } > > int > -- > 2.7.4