From: "Nélio Laranjeiro" <nelio.laranjeiro@6wind.com>
To: Yongseok Koh <yskoh@mellanox.com>
Cc: adrien.mazarguil@6wind.com, dev@dpdk.org, stable@dpdk.org,
Sagi Grimberg <sagi@grimberg.me>,
Alexander Solganik <solganik@gmail.com>
Subject: Re: [dpdk-stable] [PATCH v2] net/mlx5: fix Tx doorbell memory barrier
Date: Wed, 25 Oct 2017 11:19:34 +0200 [thread overview]
Message-ID: <20171025091934.hvf5fv4bpkzaba2u@laranjeiro-vm> (raw)
In-Reply-To: <49c39b44917c35ecaabf06f5f920d0f7e0ed0b6b.1508891141.git.yskoh@mellanox.com>
On Tue, Oct 24, 2017 at 05:27:25PM -0700, Yongseok Koh wrote:
> Configuring UAR as IO-mapped makes maximum throughput decline by noticeable
> amount. If UAR is configured as write-combining register, a write memory
> barrier is needed on ringing a doorbell. rte_wmb() is mostly effective when
> the size of a burst is comparatively small. Revert the register back to
> write-combining and enforce a write memory barrier instead, except for
> vectorized Tx burst routines. Application can change it by setting
> MLX5_SHUT_UP_BF under its own necessity.
>
> Fixes: 9f9bebae5530 ("net/mlx5: don't map doorbell register to write combining")
> Cc: stable@dpdk.org
> Cc: Sagi Grimberg <sagi@grimberg.me>
> Cc: Alexander Solganik <solganik@gmail.com>
>
> Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
> Acked-by: Shahaf Shuler <shahafs@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Thanks,
--
Nélio Laranjeiro
6WIND
next prev parent reply other threads:[~2017-10-25 9:19 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-22 8:00 [dpdk-stable] [PATCH] " Yongseok Koh
2017-10-22 9:46 ` [dpdk-stable] [dpdk-dev] " Sagi Grimberg
2017-10-22 22:01 ` Yongseok Koh
2017-10-23 7:50 ` Nélio Laranjeiro
2017-10-23 17:24 ` Yongseok Koh
2017-10-24 6:49 ` Nélio Laranjeiro
2017-10-23 7:00 ` [dpdk-stable] " Nélio Laranjeiro
2017-10-25 0:27 ` [dpdk-stable] [PATCH v2] " Yongseok Koh
2017-10-25 9:19 ` Nélio Laranjeiro [this message]
2017-10-25 21:34 ` Ferruh Yigit
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