From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by dpdk.org (Postfix) with ESMTP id B1AC61B249 for ; Mon, 30 Oct 2017 16:37:32 +0100 (CET) Received: by mail-wm0-f66.google.com with SMTP id p75so16748972wmg.3 for ; Mon, 30 Oct 2017 08:37:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=goGYLuuWKAGfaI4Rg9W8TcIFXURITV+OJnfZyHGg+gY=; b=boZgDoXLWt0RzYSLW9ghTL+YcuLv/tbaIbVLL3uuACR2izXgN4/vF+gzL4fA9NYHwv frF9C8JRrvlBQR1RjPpjHuXd2SjhXjJ36BGHV9OpKeZ4yGptIJooPU4gzOSKLplIWCbV 3XYwWfloI9zy29lyIeB8FOjeoUkRkhA7AJChdT1RzyMdZcfGcHSAoZhqKdJrkwjgaWjb XWxYWRSAzBLmdI0DzkpM43A6G4k+GLWCsKNpIF8I21PGOJLsLbEJfqm+F4KFOoaYyOnM +YWpKSBTpufyfEhKYjxyfP+SV0qurjk9U62+Uyl0mGIjWoRY3pBVlaICbaJAQ1BMIRfZ K6iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=goGYLuuWKAGfaI4Rg9W8TcIFXURITV+OJnfZyHGg+gY=; b=TZSTN4DNG1545TIYmbxNf5nE7k22iI4pmHMN/IKBApAcvyHj8H1bEOjRXc/mhFVcHV jZC1FVRo5pUTByMOekjb3tzLPH3rdPP/1SK5dqifKeRZakqnTuiKKWYpg5ABWTkC6Hoj k0GuTeQSTUk0G5isRIGxE+JfUHwI+InVXuT/ea10cOaCyKAR7+ueZl8xHHWhc7I0UZYG cB8ianjjWd/JLQGgaqXhggZzqeG6Dd5M4Fo+OnmDTPIwDQt6juhtw3831kFcbY2KTBUc X01TxzvGTRZwwpSByl/ntnlFhekVuUksGdfgn1AsJnm6XFQSIy0LPGzPXsmw7XE5+y3X k2EQ== X-Gm-Message-State: AMCzsaWfsQ5yBhOXY2n7AiDsXQw0vpZMS7JrHgu4Lqcn0K5oo5viBUmk 2p4eadHeFXzbZtPoagfdulYxLX38Om8= X-Google-Smtp-Source: ABhQp+Sxwn8TJTGEwfPWmjzpw9qlWH1BwZKPPfwgxB24DS4iP42K/kyHH9Zco2I/2nh33D1ogu7SgA== X-Received: by 10.28.225.214 with SMTP id y205mr4506491wmg.12.1509377852394; Mon, 30 Oct 2017 08:37:32 -0700 (PDT) Received: from localhost ([2a00:23c5:bef3:400:4a51:b7ff:fe0b:4749]) by smtp.gmail.com with ESMTPSA id 141sm5284612wmr.45.2017.10.30.08.37.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 30 Oct 2017 08:37:31 -0700 (PDT) From: luca.boccassi@gmail.com To: Rasesh Mody Cc: dpdk stable Date: Mon, 30 Oct 2017 15:34:29 +0000 Message-Id: <20171030153511.13322-26-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171030153511.13322-1-luca.boccassi@gmail.com> References: <20171030153511.13322-1-luca.boccassi@gmail.com> Subject: [dpdk-stable] patch 'net/qede/base: fix macros to check chip revision/metal' has been queued to LTS release 16.11.4 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Oct 2017 15:37:32 -0000 Hi, FYI, your patch has been queued to LTS release 16.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/01/17. So please shout if anyone has objections. Thanks. Kind regards, Luca Boccassi --- >>From cacebaeef1f89cc81f018211e660ecd6a1a574b9 Mon Sep 17 00:00:00 2001 From: Rasesh Mody Date: Mon, 18 Sep 2017 18:30:09 -0700 Subject: [PATCH] net/qede/base: fix macros to check chip revision/metal [ upstream commit 3b212853e478e45490668ea054ec351da1fbda43 ] Fix the ECORE_IS_[AB]0() macros to check both the chip revision and the chip metal. Realign defines in the struct ecore_dev. Fixes: ec94dbc57362 ("qede: add base driver") Signed-off-by: Rasesh Mody --- drivers/net/qede/base/ecore.h | 78 +++++++++++++++++++-------------------- drivers/net/qede/base/ecore_dev.c | 25 ++++++------- drivers/net/qede/base/ecore_vf.c | 2 +- 3 files changed, 51 insertions(+), 54 deletions(-) diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h index fce87e2f9..e2da8aaca 100644 --- a/drivers/net/qede/base/ecore.h +++ b/drivers/net/qede/base/ecore.h @@ -624,45 +624,45 @@ struct ecore_dev { u16 device_id; u16 chip_num; - #define CHIP_NUM_MASK 0xffff - #define CHIP_NUM_SHIFT 16 +#define CHIP_NUM_MASK 0xffff +#define CHIP_NUM_SHIFT 0 - u16 chip_rev; - #define CHIP_REV_MASK 0xf - #define CHIP_REV_SHIFT 12 + u8 chip_rev; +#define CHIP_REV_MASK 0xf +#define CHIP_REV_SHIFT 0 #ifndef ASIC_ONLY - #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) - #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) - #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) - #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \ - CHIP_REV_IS_EMUL_B0(_p_dev)) - #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) - #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) - #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \ - CHIP_REV_IS_FPGA_B0(_p_dev)) - #define CHIP_REV_IS_SLOW(_p_dev) \ - (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) - #define CHIP_REV_IS_A0(_p_dev) \ - (CHIP_REV_IS_EMUL_A0(_p_dev) || \ - CHIP_REV_IS_FPGA_A0(_p_dev) || \ - !(_p_dev)->chip_rev) - #define CHIP_REV_IS_B0(_p_dev) \ - (CHIP_REV_IS_EMUL_B0(_p_dev) || \ - CHIP_REV_IS_FPGA_B0(_p_dev) || \ - (_p_dev)->chip_rev == 1) - #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) +#define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) +#define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) +#define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) +#define CHIP_REV_IS_EMUL(_p_dev) \ + (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev)) +#define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) +#define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) +#define CHIP_REV_IS_FPGA(_p_dev) \ + (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev)) +#define CHIP_REV_IS_SLOW(_p_dev) \ + (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) +#define CHIP_REV_IS_A0(_p_dev) \ + (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \ + (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)) +#define CHIP_REV_IS_B0(_p_dev) \ + (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \ + ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)) +#define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) #else - #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev) - #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1) +#define CHIP_REV_IS_A0(_p_dev) \ + (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal) +#define CHIP_REV_IS_B0(_p_dev) \ + ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal) #endif - u16 chip_metal; - #define CHIP_METAL_MASK 0xff - #define CHIP_METAL_SHIFT 4 + u8 chip_metal; +#define CHIP_METAL_MASK 0xff +#define CHIP_METAL_SHIFT 0 - u16 chip_bond_id; - #define CHIP_BOND_ID_MASK 0xf - #define CHIP_BOND_ID_SHIFT 0 + u8 chip_bond_id; +#define CHIP_BOND_ID_MASK 0xff +#define CHIP_BOND_ID_SHIFT 0 u8 num_engines; u8 num_ports_in_engines; @@ -670,12 +670,12 @@ struct ecore_dev { u8 path_id; enum ecore_mf_mode mf_mode; - #define IS_MF_DEFAULT(_p_hwfn) \ - (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) - #define IS_MF_SI(_p_hwfn) \ - (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) - #define IS_MF_SD(_p_hwfn) \ - (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) +#define IS_MF_DEFAULT(_p_hwfn) \ + (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) +#define IS_MF_SI(_p_hwfn) \ + (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) +#define IS_MF_SD(_p_hwfn) \ + (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) int pcie_width; int pcie_speed; diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c index 76255bd01..d2dc044dc 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -2856,12 +2856,10 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev) else p_dev->type = ECORE_DEV_TYPE_BB; - p_dev->chip_num = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, - MISCS_REG_CHIP_NUM); - p_dev->chip_rev = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, - MISCS_REG_CHIP_REV); - - MASK_FIELD(CHIP_REV, p_dev->chip_rev); + tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, MISCS_REG_CHIP_NUM); + p_dev->chip_num = (u16)GET_FIELD(tmp, CHIP_NUM); + tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, MISCS_REG_CHIP_REV); + p_dev->chip_rev = (u8)GET_FIELD(tmp, CHIP_REV); /* Learn number of HW-functions */ tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, @@ -2885,20 +2883,19 @@ static enum _ecore_status_t ecore_get_dev_info(struct ecore_dev *p_dev) } #endif - p_dev->chip_bond_id = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, - MISCS_REG_CHIP_TEST_REG) >> 4; - MASK_FIELD(CHIP_BOND_ID, p_dev->chip_bond_id); - p_dev->chip_metal = (u16)ecore_rd(p_hwfn, p_hwfn->p_main_ptt, - MISCS_REG_CHIP_METAL); - MASK_FIELD(CHIP_METAL, p_dev->chip_metal); + tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, MISCS_REG_CHIP_TEST_REG); + p_dev->chip_bond_id = (u8)GET_FIELD(tmp, CHIP_BOND_ID); + tmp = ecore_rd(p_hwfn, p_hwfn->p_main_ptt, MISCS_REG_CHIP_METAL); + p_dev->chip_metal = (u8)GET_FIELD(tmp, CHIP_METAL); + DP_INFO(p_dev->hwfns, - "Chip details - %s%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", + "Chip details - %s%d, Num: %04x Rev: %02x Bond id: %02x Metal: %02x\n", ECORE_IS_BB(p_dev) ? "BB" : "AH", CHIP_REV_IS_A0(p_dev) ? 0 : 1, p_dev->chip_num, p_dev->chip_rev, p_dev->chip_bond_id, p_dev->chip_metal); - if (ECORE_IS_BB(p_dev) && CHIP_REV_IS_A0(p_dev)) { + if (ECORE_IS_BB_A0(p_dev)) { DP_NOTICE(p_dev->hwfns, false, "The chip type/rev (BB A0) is not supported!\n"); return ECORE_ABORTED; diff --git a/drivers/net/qede/base/ecore_vf.c b/drivers/net/qede/base/ecore_vf.c index be8b1ec4e..5ff8f28a4 100644 --- a/drivers/net/qede/base/ecore_vf.c +++ b/drivers/net/qede/base/ecore_vf.c @@ -325,7 +325,7 @@ static enum _ecore_status_t ecore_vf_pf_acquire(struct ecore_hwfn *p_hwfn) /* get HW info */ p_hwfn->p_dev->type = resp->pfdev_info.dev_type; - p_hwfn->p_dev->chip_rev = resp->pfdev_info.chip_rev; + p_hwfn->p_dev->chip_rev = (u8)resp->pfdev_info.chip_rev; DP_INFO(p_hwfn, "Chip details - %s%d\n", ECORE_IS_BB(p_hwfn->p_dev) ? "BB" : "AH", -- 2.11.0