From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by dpdk.org (Postfix) with ESMTP id BB0E21B252 for ; Mon, 30 Oct 2017 16:38:17 +0100 (CET) Received: by mail-wm0-f66.google.com with SMTP id z3so17299790wme.5 for ; Mon, 30 Oct 2017 08:38:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JI4u3jm/dPsTEGnr5LNldH7SExt65Hb/bc7MIxVvyDg=; b=XCIwY2EYSX3YC+0kMN1PPK7PxGEbhM3ZyXybzN2ayCy1V91xBYUhfpeX3g9fS2t+LT X9wggTLwVenkWrkq9KF8th2TBI4SqLmZMkHhpxeYJ84YL6vbaWkEIcnO3tXEOnHdcpDP +8n3HLkVRmPmfEiifwaPOVKzLD0aUa6sky4nFnAUk01t/qJrMgb3HdlKv5g9On9iURc3 sX2pHEHWMob7GN1bGCUeJsl7S/xIa/gq99yf+xon52NiE/gSJh2BqDhxHQNQNdTXNys2 LolqMxKi8exIZDsNc2JcMzJRstrcTidXB52vADx2kncuQKph+/JZWyszYaukMqM/Ts2Q KFPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JI4u3jm/dPsTEGnr5LNldH7SExt65Hb/bc7MIxVvyDg=; b=by1A3tZyKrTCKI5pASVb3EkTiQEyhw3mG7nt9bpaLA8ME62FV7Vxzfz1Hk1xtbzu8v swEYzZbOX2bYjBGgHOug3C+YptF4CeCY6wKE3Fs8gx+8gIRLu3K9hMjhqMZxyrD7G/Ma UYr+Ho4qcjykqP8oLfFGTMjtBg4f/4kikduj+hLsF8O/eqYUaybLvXCsPawsVUutZ4gr VWXPSSXaahw4IfAjjKsbCZyEvlOo2yEcALYTQ1iDWJpi6COC6o1C7UELXsYn7tycLJV2 kaar7fSimmUvS3u9URse/B0uFCc4H6OzjtuZkTYyHAORvHWVCVKDxCHvPEH7mR2Gtx/D brhQ== X-Gm-Message-State: AMCzsaUcMvPoc5rdd5I2c4ffD48tLGWW4jDDyf6WQILOE07vd5C87smY IohAKXH6Sj98Lqpr6Xhq/UVeK+wV4N8= X-Google-Smtp-Source: ABhQp+TADeIrcQmXCo5Vf80vQoBBcomXjxSVL7S9iOXzSRBiqIGdML51YGIdy224ZHPxmcc+GT8OnQ== X-Received: by 10.28.167.130 with SMTP id q124mr3932862wme.136.1509377897503; Mon, 30 Oct 2017 08:38:17 -0700 (PDT) Received: from localhost ([2a00:23c5:bef3:400:4a51:b7ff:fe0b:4749]) by smtp.gmail.com with ESMTPSA id x65sm1121650wmg.11.2017.10.30.08.38.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 30 Oct 2017 08:38:16 -0700 (PDT) From: luca.boccassi@gmail.com To: Andrey Chilikin Cc: Beilei Xing , dpdk stable Date: Mon, 30 Oct 2017 15:35:01 +0000 Message-Id: <20171030153511.13322-58-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171030153511.13322-1-luca.boccassi@gmail.com> References: <20171030153511.13322-1-luca.boccassi@gmail.com> Subject: [dpdk-stable] patch 'net/i40e: fix flexible payload configuration' has been queued to LTS release 16.11.4 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Oct 2017 15:38:17 -0000 Hi, FYI, your patch has been queued to LTS release 16.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/01/17. So please shout if anyone has objections. Thanks. Kind regards, Luca Boccassi --- >>From 0b35308e321ff94a28088b0e6ee6f922a60223f9 Mon Sep 17 00:00:00 2001 From: Andrey Chilikin Date: Fri, 6 Oct 2017 19:11:26 +0100 Subject: [PATCH] net/i40e: fix flexible payload configuration [ upstream commit 1edc13a83b0d41f7ab982996f5a1ef9c5ee13b7b ] Removed legacy writes to ORT/PIT registers from i40e_GLQF_reg_init(struct i40e_hw *hw) function. Latest NVM versions contain all relevant values and these values should not be overwritten by SW to maintain driver/firmware compatibility and to avoid conflicts with dynamic device personalization profiles. Fixes: f05ec7d77e41 ("i40e: initialize flow director flexible payload setting") Signed-off-by: Andrey Chilikin Acked-by: Beilei Xing --- drivers/net/i40e/i40e_ethdev.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index d63d5b483..43bd0a4f3 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -729,23 +729,22 @@ RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map); static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) { /* - * Initialize registers for flexible payload, which should be set by NVM. - * This should be removed from code once it is fixed in NVM. + * Force global configuration for flexible payload + * to the first 16 bytes of the corresponding L2/L3/L4 paylod. + * This should be removed from code once proper + * configuration API is added to avoid configuration conflicts + * between ports of the same device. */ - I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030); - I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030); - I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B); - I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B); I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0); I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3); I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6); - I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031); - I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031); - I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D); - I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480); - I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440); - /* Initialize registers for parsing packet type of QinQ */ + /* + * Initialize registers for parsing packet type of QinQ + * This should be removed from code once proper + * configuration API is added to avoid configuration conflicts + * between ports of the same device. + */ I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029); I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420); } -- 2.11.0