From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by dpdk.org (Postfix) with ESMTP id 29EA41B70C for ; Fri, 10 Nov 2017 17:10:21 +0100 (CET) Received: by mail-wm0-f68.google.com with SMTP id r68so3738023wmr.1 for ; Fri, 10 Nov 2017 08:10:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Q9RGJ9Hsk3r+JxNhYbL48e0Y0q26SXI/oXL8VUUUDPY=; b=ECNJ0TPjjz8uGZEyDurP8deLvpGREE4rc1DsvbB8DHo7A2dbCHdQuNPR/6Ave4X2Ho GzpsGgE3seyga2pPUPJKPWZEP7xQbAxlYJ3DtiDu2GHFDYx1XA7gnHTpo2EGgVoW2iL3 6WFdqSWBlzNGe0xLTHc6sloW7RnzsReQacv1FB439ABbTMUP/YhGz9YQeObxjZi4sgLV V7mK72M2gdjziRTgv6u/jLuOVbYngUKXpZrY2B3cqwC3TlEOtmaGg8cV5LKW/Xa/0Xz2 0jwH1i10/2PplNMdpw+D43xDh+SbNrounJrbBsxq8UFEYa9QaOS37zkSBzDPiKe+Zmwn UEwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Q9RGJ9Hsk3r+JxNhYbL48e0Y0q26SXI/oXL8VUUUDPY=; b=DF0QQQkeSPI2HLz6GAZyfuprLlm/0dv6YD9HINxPvrcu0uCfLyucJ2dwuw567MNjaM Ex/+WBTdYF7TfGP/ObU2ZStPedA1pxIxmbh3DJeGenWLG3DEzNr+deJBkzMdOLroAsQW prvlaLNCRDQajjKUyf/D5rmHZWKtYP0woOUtnKpTPOjs9OT+5yd6EdItNXdc2CL+RPNx hs3Y0ZLNTkDHUMEFMY5dpKREjp/RydrNYlsSslv9JobqfFGm2Yl+jw6hp4cl5CSkjSST 2T6CaaamMDcH6EJl2Wl6nFZCj/41GD8eb8JPL9A8c5FM2oeFpaHgy8CYCi+jkvz6KA+6 SXRw== X-Gm-Message-State: AJaThX6uUZBJKzAi+B/AwaKPr+x2E4IsBU5OXEB/IuGGso0om5P+52eY m1LWpOoMQFK9P7Rm+4yXljw= X-Google-Smtp-Source: AGs4zMbUVQ8dmOEyxT+qHBLQKy4gPrMadTU3a1vwfN9qtjkKsruecQ/benrSxdKzm1rz7ZeZ1qCc2g== X-Received: by 10.28.103.8 with SMTP id b8mr712354wmc.70.1510330220875; Fri, 10 Nov 2017 08:10:20 -0800 (PST) Received: from localhost ([2a00:23c5:bef3:400:4a51:b7ff:fe0b:4749]) by smtp.gmail.com with ESMTPSA id q13sm3813514wrg.97.2017.11.10.08.10.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 10 Nov 2017 08:10:20 -0800 (PST) From: luca.boccassi@gmail.com To: Xiaoyun Li Cc: Wenzhuo Lu , dpdk stable Date: Fri, 10 Nov 2017 16:09:52 +0000 Message-Id: <20171110161000.15369-8-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171110161000.15369-1-luca.boccassi@gmail.com> References: <20171102120247.10565-18-luca.boccassi@gmail.com> <20171110161000.15369-1-luca.boccassi@gmail.com> Subject: [dpdk-stable] patch 'net/igb: fix Rx interrupt with VFIO and MSI-X' has been queued to LTS release 16.11.4 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Nov 2017 16:10:21 -0000 Hi, FYI, your patch has been queued to LTS release 16.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/12/17. So please shout if anyone has objections. Thanks. Kind regards, Luca Boccassi --- >>From 574f0413aabb6ec17d0bd155869fdf738946103c Mon Sep 17 00:00:00 2001 From: Xiaoyun Li Date: Mon, 6 Nov 2017 10:41:40 +0800 Subject: [PATCH] net/igb: fix Rx interrupt with VFIO and MSI-X [ upstream commit 88e04712f40fca9dd3ab98dd549e27791c320b75 ] When using VFIO and MSIX interrupt mode, cannot get Rx interrupts. Because when enabling the interrupt vectors, the offset is computed in a way which only supports IGB_UIO. But the offset should be different when using VFIO. This patch fixes this issue. Fixes: c3cd3de0ab50 ("igb: enable Rx queue interrupts for PF") Signed-off-by: Xiaoyun Li Acked-by: Wenzhuo Lu --- drivers/net/e1000/igb_ethdev.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index d16be9e1b..407021dfe 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -5095,7 +5095,13 @@ eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) { struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t mask = 1 << queue_id; + struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; + uint32_t vec = E1000_MISC_VEC_ID; + + if (rte_intr_allow_others(intr_handle)) + vec = E1000_RX_VEC_START; + + uint32_t mask = 1 << (queue_id + vec); E1000_WRITE_REG(hw, E1000_EIMC, mask); E1000_WRITE_FLUSH(hw); @@ -5108,7 +5114,13 @@ eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) { struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint32_t mask = 1 << queue_id; + struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; + uint32_t vec = E1000_MISC_VEC_ID; + + if (rte_intr_allow_others(intr_handle)) + vec = E1000_RX_VEC_START; + + uint32_t mask = 1 << (queue_id + vec); uint32_t regval; regval = E1000_READ_REG(hw, E1000_EIMS); -- 2.11.0