From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id D8C103257; Fri, 12 Jan 2018 11:23:03 +0100 (CET) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8064AB2AB; Fri, 12 Jan 2018 10:23:02 +0000 (UTC) Received: from localhost.localdomain (ovpn-112-28.ams2.redhat.com [10.36.112.28]) by smtp.corp.redhat.com (Postfix) with ESMTP id 432635D6A6; Fri, 12 Jan 2018 10:22:33 +0000 (UTC) From: Maxime Coquelin To: dev@dpdk.org, stable@dpdk.org, jianfeng.tan@intel.com, qi.z.zhang@intel.com, stephen@networkplumber.org, santosh.shukla@caviumnetworks.com, anatoly.burakov@intel.com, thomas@monjalon.net Cc: peterx@redhat.com, Maxime Coquelin Date: Fri, 12 Jan 2018 11:22:20 +0100 Message-Id: <20180112102220.20061-1-maxime.coquelin@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Fri, 12 Jan 2018 10:23:02 +0000 (UTC) Subject: [dpdk-stable] [PATCH v3] bus/pci: forbid VA as IOVA mode if IOMMU address width too small X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Jan 2018 10:23:04 -0000 Intel VT-d supports different address widths for the IOVAs, from 39 bits to 56 bits. While recent processors support at least 48 bits, VT-d emulation currently only supports 39 bits. It makes DMA mapping to fail in this case when using VA as IOVA mode, as user-space virtual addresses uses up to 47 bits (see kernel's Documentation/x86/x86_64/mm.txt). This patch parses VT-d CAP register value available in sysfs, and forbid VA as IOVA mode if the GAW is 39 bits or unknown. Fixes: f37dfab21c98 ("drivers/net: enable IOVA mode for Intel PMDs") Cc: stable@dpdk.org Signed-off-by: Maxime Coquelin --- Changes in v3: ============== - Rely on MGAW bitfiled instead of SAGAW (Qi) Changes in v2: ============== - Rework pci_one_device_iommu_support_va #ifdefery (Stephen) - Don't inline introduced functions (Stephen) drivers/bus/pci/linux/pci.c | 90 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 81 insertions(+), 9 deletions(-) diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c index 25f907e04..a89e8353d 100644 --- a/drivers/bus/pci/linux/pci.c +++ b/drivers/bus/pci/linux/pci.c @@ -547,6 +547,82 @@ pci_one_device_has_iova_va(void) return 0; } +#if defined(RTE_ARCH_X86) +static bool +pci_one_device_iommu_support_va(struct rte_pci_device *dev) +{ +#define VTD_CAP_MGAW_SHIFT 16 +#define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT) +#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */ + struct rte_pci_addr *addr = &dev->addr; + char filename[PATH_MAX]; + FILE *fp; + uint64_t mgaw, vtd_cap_reg = 0; + + snprintf(filename, sizeof(filename), + "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap", + rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid, + addr->function); + if (access(filename, F_OK) == -1) { + /* We don't have an Intel IOMMU, assume VA supported*/ + return true; + } + + /* We have an intel IOMMU */ + fp = fopen(filename, "r"); + if (fp == NULL) { + RTE_LOG(ERR, EAL, "%s(): can't open %s\n", __func__, filename); + return false; + } + + if (fscanf(fp, "%lx", &vtd_cap_reg) != 1) { + RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename); + fclose(fp); + return false; + } + + fclose(fp); + + mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1; + if (mgaw < X86_VA_WIDTH) + return false; + + return true; +} +#elif defined(RTE_ARCH_PPC_64) +static bool +pci_one_device_iommu_support_va(struct rte_pci_device *dev) +{ + return false; +} +#else +static bool +pci_one_device_iommu_support_va(struct rte_pci_device *dev) +{ + return true; +} +#endif + +/* + * All devices IOMMUs support VA as IOVA + */ +static bool +pci_devices_iommu_support_va(void) +{ + struct rte_pci_device *dev = NULL; + struct rte_pci_driver *drv = NULL; + + FOREACH_DRIVER_ON_PCIBUS(drv) { + FOREACH_DEVICE_ON_PCIBUS(dev) { + if (!rte_pci_match(drv, dev)) + continue; + if (!pci_one_device_iommu_support_va(dev)) + return false; + } + } + return true; +} + /* * Get iommu class of PCI devices on the bus. */ @@ -557,12 +633,7 @@ rte_pci_get_iommu_class(void) bool is_vfio_noiommu_enabled = true; bool has_iova_va; bool is_bound_uio; - bool spapr_iommu = -#if defined(RTE_ARCH_PPC_64) - true; -#else - false; -#endif + bool iommu_no_va; is_bound = pci_one_device_is_bound(); if (!is_bound) @@ -570,13 +641,14 @@ rte_pci_get_iommu_class(void) has_iova_va = pci_one_device_has_iova_va(); is_bound_uio = pci_one_device_bound_uio(); + iommu_no_va = !pci_devices_iommu_support_va(); #ifdef VFIO_PRESENT is_vfio_noiommu_enabled = rte_vfio_noiommu_is_enabled() == true ? true : false; #endif if (has_iova_va && !is_bound_uio && !is_vfio_noiommu_enabled && - !spapr_iommu) + !iommu_no_va) return RTE_IOVA_VA; if (has_iova_va) { @@ -585,8 +657,8 @@ rte_pci_get_iommu_class(void) RTE_LOG(WARNING, EAL, "vfio-noiommu mode configured\n"); if (is_bound_uio) RTE_LOG(WARNING, EAL, "few device bound to UIO\n"); - if (spapr_iommu) - RTE_LOG(WARNING, EAL, "sPAPR IOMMU does not support IOVA as VA\n"); + if (iommu_no_va) + RTE_LOG(WARNING, EAL, "IOMMU does not support IOVA as VA\n"); } return RTE_IOVA_PA; -- 2.14.3