From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by dpdk.org (Postfix) with ESMTP id 8086A1B756 for ; Wed, 7 Feb 2018 17:47:41 +0100 (CET) Received: by mail-wm0-f67.google.com with SMTP id 143so4343273wma.5 for ; Wed, 07 Feb 2018 08:47:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lLlvJHMGpQXS+GgsD9oc8Un0PYl+SZs1xgdsVsjreQ4=; b=RKY0/d7Hks6hNaQCXl6RDGDPOxGU27hXIzJtpoZS479DTEsYPYd6rxNiaWfSklgAyF /zvoFR8pB+dT/Br38llNrQKsQhvHi5ayLSkNZqdGrNZXjH3YNNKYMF6xA9diAVM/1wf8 8MRY4Mk/7WdL2NXpEWQu/iOQ9tmxCYN/Obo4k4wCJVxGGFdaSFuljmQE//AQE1P6NW/H RyokpV6uvfKZpvO8Zzir58+6w+aSU2y9neL4c4vcm6hW4oJ+b/sb1S0IsKgkyC9HBepZ PAR1u5uwZOD5viOrelv0Vwc7Q9aY0GqxsZbfnlHw1Lm7QWlSAOcF78QNkxIiTSBlDgDG arPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lLlvJHMGpQXS+GgsD9oc8Un0PYl+SZs1xgdsVsjreQ4=; b=TKb1mq8TqE5YJsOzgVCD7GYPWdDXOHxPKnOzI17+hVJjck59dOCYWS+0Db9GfbXFFI FuEuQ40Aq5W/2an7ciZqymDbKXC81n17af5EW8hQKG+TpzyU2Oe577i+KVLRaIS32fkH +9nnsff5bcBiA1zjchQBCidHKvEbLfI/kEUCVcTYqEVs6Wg+u69YEouxtu5NB1g7+tR0 qRRD0TFICAZP5DHhw0ajJ4sHK8/8RiAccwWbo5gcY7RngxKXDh8VGJTtZGx3y9bAsmRq hcEnIx707z3dOd0DYq/PYFf47sDPIWmkhew7Ds5ThfGyER4ifia5Gdb8eiFBUxHB4NVR C78Q== X-Gm-Message-State: APf1xPCTqJa13+lMr22e1xoJIYuRsCiZxOxtctS54gnOOtIhjmkcXc1T 0W6Yod2VdBJPvG4rcd6xSTN3D5GUxMQ= X-Google-Smtp-Source: AH8x226Nl+IhUmbphbOUn85wv65NZptB/jW0bRPYXPmN9kOEwI+xGKVu873t6p1Ig974Up7uhjs3mg== X-Received: by 10.28.118.15 with SMTP id r15mr5798259wmc.88.1518022061246; Wed, 07 Feb 2018 08:47:41 -0800 (PST) Received: from localhost ([2a00:23c5:bef3:400:9531:588b:44ae:bec4]) by smtp.gmail.com with ESMTPSA id p10sm3154418wrh.96.2018.02.07.08.47.40 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 07 Feb 2018 08:47:40 -0800 (PST) From: luca.boccassi@gmail.com To: Gowrishankar Muthukrishnan Cc: dpdk stable Date: Wed, 7 Feb 2018 16:46:48 +0000 Message-Id: <20180207164705.29052-17-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180207164705.29052-1-luca.boccassi@gmail.com> References: <20180126131332.15346-62-luca.boccassi@gmail.com> <20180207164705.29052-1-luca.boccassi@gmail.com> Subject: [dpdk-stable] patch 'eal/ppc: remove the braces in memory barrier macros' has been queued to LTS release 16.11.5 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Feb 2018 16:47:41 -0000 Hi, FYI, your patch has been queued to LTS release 16.11.5 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 02/09/18. So please shout if anyone has objections. Thanks. Luca Boccassi --- >>From 31f13165af00c0cd118565274ef26d1d2b70f941 Mon Sep 17 00:00:00 2001 From: Gowrishankar Muthukrishnan Date: Tue, 30 Jan 2018 16:23:18 +0530 Subject: [PATCH] eal/ppc: remove the braces in memory barrier macros [ upstream commit 257515a50057fa97605cc13e5b3b9cc9f964c299 ] Calling rte_smp_{w/r}mb macro expands into a compound block, which would break compiling a else clause following it, if that calling place has been terminated already with ";", as in below code. This patch adds { } around this macro to allow compiling else too. Fixes: d23a6bd04d ("eal/ppc: fix memory barrier for IBM POWER") Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power") Signed-off-by: Gowrishankar Muthukrishnan --- lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h index fb4fccb48..37f5eff20 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h @@ -64,9 +64,9 @@ extern "C" { * occur before the STORE operations generated after. */ #ifdef RTE_ARCH_64 -#define rte_wmb() {asm volatile("lwsync" : : : "memory"); } +#define rte_wmb() asm volatile("lwsync" : : : "memory") #else -#define rte_wmb() {asm volatile("sync" : : : "memory"); } +#define rte_wmb() asm volatile("sync" : : : "memory") #endif /** @@ -76,9 +76,9 @@ extern "C" { * occur before the LOAD operations generated after. */ #ifdef RTE_ARCH_64 -#define rte_rmb() {asm volatile("lwsync" : : : "memory"); } +#define rte_rmb() asm volatile("lwsync" : : : "memory") #else -#define rte_rmb() {asm volatile("sync" : : : "memory"); } +#define rte_rmb() asm volatile("sync" : : : "memory") #endif #define rte_smp_mb() rte_mb() -- 2.14.2