From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by dpdk.org (Postfix) with ESMTP id B44311B74A for ; Wed, 7 Feb 2018 17:48:08 +0100 (CET) Received: by mail-wr0-f196.google.com with SMTP id w50so1774440wrc.2 for ; Wed, 07 Feb 2018 08:48:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MT9pmZyOMRuJF/eaDsYsU9EIQei1ZQ/0Nb7CvOHkVwE=; b=DdXH7HysUwNT2hfPM4dC8L5odi0jR+Vd3fN7ji+GCCyOJT6Fw1LEhr3rHEJNuL9wJt YJyMfNSE6gPWSOnbtEfC+1Z1qGS/veMUJ3JmX2C5brLEqqmIlniHoVkFUwXBlDy4koxs HQcSPIvDIUy5z7ZBeYm9mGwCJjWYrKFOu7QjAtQYzkhwHlLw7HoE6mC8Ek/q4+GNZTh8 BvEe/1JpsWX6max/3fLJSIAwVhlYFJQBiaiJoZbg23u0You4/R2R9LUEq2bPXpEz1A/o npRCD5SCozo3mDWXKTthPH/P9AKNQhHPl/RXUR3ALIknRgiWt5vSAOho8NAY/n8bl9RC Cc1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MT9pmZyOMRuJF/eaDsYsU9EIQei1ZQ/0Nb7CvOHkVwE=; b=L8xHktwxHiJIPQqcrhw6LbOungG3b6wBn3v+MsBIuRt1iWBfqotGYKDIKvugAiwf23 Uci/MfQdkq9F01A+0dUjiP7QYusbY/ce03uN63rtfIC3vi1iuqaakua6wzpnT+zinKL0 TUEuEx7gO4gJPNS/JIQdFMueVwBpDaGcGDcDoE+RXOk2es+pqPN21BUHAX3xlF+hCRe/ b7byJPfa+7u/7lTn0JS/J0ssV3IyYBnlizoNp53+WPnJLNxGtya68Mzr4AD953igXGgL gieXvYQrEdJj/gEWIrBcJCG9MpqASmWp+35lnpDv07RjYZhGz3LzRzfqW0j3vLpbgCZG ddrg== X-Gm-Message-State: APf1xPBBijYiVkZfT6NS+nmpwF1UQXZSaAPqXHd8O9afEG1SiwIlUzp7 BZVC2bYtSfjnJbNZnjZ7a3Ptv5qJ08M= X-Google-Smtp-Source: AH8x22617kqLYqHPqmY7QtnVlBqiglnUfi2pTBGKC9ucSIlPzvcaSwIo/nO+Z1Pb9ZMGUBafwmxlMQ== X-Received: by 10.223.184.200 with SMTP id c8mr6380146wrg.105.1518022088452; Wed, 07 Feb 2018 08:48:08 -0800 (PST) Received: from localhost ([2a00:23c5:bef3:400:9531:588b:44ae:bec4]) by smtp.gmail.com with ESMTPSA id m11sm2117515wrf.75.2018.02.07.08.48.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 07 Feb 2018 08:48:07 -0800 (PST) From: luca.boccassi@gmail.com To: Beilei Xing Cc: Helin Zhang , dpdk stable Date: Wed, 7 Feb 2018 16:47:05 +0000 Message-Id: <20180207164705.29052-34-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180207164705.29052-1-luca.boccassi@gmail.com> References: <20180126131332.15346-62-luca.boccassi@gmail.com> <20180207164705.29052-1-luca.boccassi@gmail.com> Subject: [dpdk-stable] patch 'net/i40e: fix Rx interrupt' has been queued to LTS release 16.11.5 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Feb 2018 16:48:08 -0000 Hi, FYI, your patch has been queued to LTS release 16.11.5 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 02/09/18. So please shout if anyone has objections. Thanks. Luca Boccassi --- >>From 1f903ee2546e72a066c291c08b560c9d712b020f Mon Sep 17 00:00:00 2001 From: Beilei Xing Date: Tue, 6 Feb 2018 13:33:31 +0800 Subject: [PATCH] net/i40e: fix Rx interrupt [ upstream commit 378cc7f569a678e1c8469094104b757864c4ad05 ] This patch fixes interval error and corrects macros when enabling Rx interrupt mode. The patch also fixes a logical error during supporting multiple drivers. Fixes: cfdfca493cae ("net/i40e: fix multiple driver support") Signed-off-by: Beilei Xing Acked-by: Helin Zhang --- drivers/net/i40e/i40e_ethdev.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index ba1120aa1..6df9b4600 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -9885,31 +9885,23 @@ i40e_dev_get_dcb_info(struct rte_eth_dev *dev, static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) { - struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle; struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); - uint16_t interval = - i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, - pf->support_multi_driver); uint16_t msix_intr; msix_intr = intr_handle->intr_vec[queue_id]; if (msix_intr == I40E_MISC_VEC_ID) I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, - I40E_PFINT_DYN_CTLN_INTENA_MASK | - I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | - (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | - (interval << - I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT)); + I40E_PFINT_DYN_CTL0_INTENA_MASK | + I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | + I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); else I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - I40E_RX_VEC_START), I40E_PFINT_DYN_CTLN_INTENA_MASK | I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | - (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) | - (interval << - I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT)); + I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); I40E_WRITE_FLUSH(hw); rte_intr_enable(&dev->pci_dev->intr_handle); @@ -9926,12 +9918,13 @@ i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) msix_intr = intr_handle->intr_vec[queue_id]; if (msix_intr == I40E_MISC_VEC_ID) - I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0); + I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, + I40E_PFINT_DYN_CTL0_ITR_INDX_MASK); else I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - I40E_RX_VEC_START), - 0); + I40E_PFINT_DYN_CTLN_ITR_INDX_MASK); I40E_WRITE_FLUSH(hw); return 0; -- 2.14.2