From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by dpdk.org (Postfix) with ESMTP id 318F5200 for ; Mon, 30 Apr 2018 16:06:29 +0200 (CEST) Received: by mail-wm0-f65.google.com with SMTP id j4so13401297wme.1 for ; Mon, 30 Apr 2018 07:06:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7mJs6bXeNo9pf4lYWCu98MngwGkFwDnhuEECzLK/PKQ=; b=bh2JHyFuSEXsBS6CHhMbASB+DRyUtAjjzpZ//aC4FSCQw+CvPQAQeAbNymSf9sy277 V6joa7gxQgldWT7ioNYbZKVC7Eyu9IPiCAHWeZFloLjYDS8QnhKdRFx7/PIK+e5t7MH/ fRGuKfZPi/zj4VjPPsTQz2kUXivRwSL4Y55QAQyG1rVN1Lbwu3mrr89NG/lGw67Je6LG urX5ubz+R7DG0aZvVE1ojtHFp5WzP+m1teUrtmtgRtsVgORrK/JNoRI5PBMPAvnJkxzW 9QMryp70yWGbYamPUwdT3wFHkbvwy6AQRqW2zEknOMN1Fe4MI3CJ55f6s4gElOqXad+I z7tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7mJs6bXeNo9pf4lYWCu98MngwGkFwDnhuEECzLK/PKQ=; b=IYKtEO6HoHxDYCbLFR0h6E1xzNkaLbY+88NaSuOmo7sF2vgM9cF7iyhCAyQ3/qxGsT QnYpt7lMssb2q8sCqZleI0yJJT37D5A3QTdQghrEZKj6nLraU5pdANgWRQFVqaUUlFbp KM2GBSLOaIzwsx2yNez6GWZ8FilwvGxquseEOtBOAWnMmDZGCagkEwk1A3zV8mC+KDvu BdwokZTKkBX0Z858aj4cW2hRsgtgdG3RfSGULAbXSq7is+kDlNO7s6xbXKyAc0JR427r yRQ6eJuXt6urNZVu0Vy1y1V/N1pdU2ttz6lFNHsC1B4hpSiloBxTDyT7paiZamYcRXNv l0vw== X-Gm-Message-State: ALQs6tCKV2f2h4b3175AsrnHVL3cpr+Tv/8o4a4lsSmLVudkziO7KFck +PRcI0lHa4hn3Ta9hMdsreY= X-Google-Smtp-Source: AB8JxZrFomoxCKmlD1IgrH0LIOUfo8zJp6ChsIl0dEDjewrAgvjj6gPfNdPWejpu+UY9Uf7ZNcjZvA== X-Received: by 10.28.158.194 with SMTP id h185mr8060999wme.68.1525097188587; Mon, 30 Apr 2018 07:06:28 -0700 (PDT) Received: from localhost ([2a00:23c5:be9a:5200:ce4c:82c0:d567:ecbb]) by smtp.gmail.com with ESMTPSA id w11-v6sm15798611wrn.86.2018.04.30.07.06.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 30 Apr 2018 07:06:27 -0700 (PDT) From: luca.boccassi@gmail.com To: Gowrishankar Muthukrishnan Cc: Luca Boccassi , Chao Zhu , dpdk stable Date: Mon, 30 Apr 2018 15:02:40 +0100 Message-Id: <20180430140606.4615-2-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180430140606.4615-1-luca.boccassi@gmail.com> References: <20180430140606.4615-1-luca.boccassi@gmail.com> Subject: [dpdk-stable] patch 'eal/ppc: remove braces in SMP memory barrier macro' has been queued to stable release 18.02.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Apr 2018 14:06:29 -0000 Hi, FYI, your patch has been queued to stable release 18.02.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/02/18. So please shout if anyone has objections. Thanks. Luca Boccassi --- >>From 1d273caf24da2902a7b4fe35f13c89b4f331ab42 Mon Sep 17 00:00:00 2001 From: Gowrishankar Muthukrishnan Date: Tue, 27 Feb 2018 20:43:58 +0530 Subject: [PATCH] eal/ppc: remove braces in SMP memory barrier macro [ upstream commit da07658d58461bef714afc196569cf18377073e2 ] This patch fixes the compilation problem with rte_smp_mb, when there is else clause following it, as in test_barrier.c. Fixes: 05c3fd7110 ("eal/ppc: atomic operations for IBM Power") Signed-off-by: Gowrishankar Muthukrishnan Acked-by: Luca Boccassi Acked-by: Chao Zhu --- lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h index 39fce7b93..182177403 100644 --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h @@ -55,7 +55,7 @@ extern "C" { * Guarantees that the LOAD and STORE operations generated before the * barrier occur before the LOAD and STORE operations generated after. */ -#define rte_mb() {asm volatile("sync" : : : "memory"); } +#define rte_mb() asm volatile("sync" : : : "memory") /** * Write memory barrier. -- 2.14.2