From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by dpdk.org (Postfix) with ESMTP id 7831F1B868 for ; Tue, 15 May 2018 15:49:37 +0200 (CEST) Received: by mail-wm0-f65.google.com with SMTP id j4-v6so1194147wme.1 for ; Tue, 15 May 2018 06:49:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5CDlYnufu/jnGl/GBl2wo/MEzzo8yweJLM4vR2bCM44=; b=O9Jj9m2+5K9cemUQzZza99fEYDav7JLQEgbkazAvWq2DcPRPEG2vBL3rFjneJAWm92 w52YWFChr/xN+zmLgbOo0phfDOLK9gpi6E8S/GkfEpEJ/mLLj/S2bjHw3FO+EyFNT9KQ VtDaTYigO5VtGRZxi7N7tmkb9dWN9L1lCG3zzrm0MvYDImADrJ4pKGu0x4jbah3IoPPt iGun49L/4/CB6i4n4+v70wvbiwOsyAMvRUMCXDvwF34Vl/x2VXRNj1qJDdlSynBf+xUU +aBdcQ1qcJBijHHkJUyj+8BL3AmnmtmXlz/qnIuv73BDYWLplj0RLGQT3EhgcUMdCTE+ 7BMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5CDlYnufu/jnGl/GBl2wo/MEzzo8yweJLM4vR2bCM44=; b=Mly28UAsXDfRhfpg4AHcf4Eswp02zeMt9CB5aL/QfHK6c+Jj5Q7fsi8hwYDtLq+GuH q+fSJfv18+4rwOdFNP9OKtl0hdmyXQ70SBBZAJQ5nGllH1M7SvWdF+K33V05Cjemws60 mOVAyXjZ349OZpYQTNKGQBsTyGQFXsNq/kAp36IxogwUl0+aFirTbiKYxWTS3SIReR5n gVnd7jGJvGmGuFunJHGAkxXhJiwyjNBGZvCChOJ4dsGlivv8XdqW9dkA1euVM1VpKYKa YcGoIgzpGo/X7WqLzhU7KfRhYy24gzxSQoZ72yf+Y8zulqEo7rzVchu1x0gzTokbyrjk ENvw== X-Gm-Message-State: ALKqPwfQqCP47TmefJtt/WttUVkDvIEuylSSpW6XQQAoO2UnGLPsexof zcblxhmxNHCXwVXjsvkNyIhPHJ/s5aw= X-Google-Smtp-Source: AB8JxZqpMMpP2P8ds2tsS5yGUAAjn9FpSrTh49OQMND0Uvh8hJvP9v2SUXNlxAY+TNDfRrd9yRbFHg== X-Received: by 2002:a1c:512:: with SMTP id 18-v6mr7659249wmf.47.1526392177158; Tue, 15 May 2018 06:49:37 -0700 (PDT) Received: from localhost (slip139-92-244-193.lon.uk.prserv.net. [139.92.244.193]) by smtp.gmail.com with ESMTPSA id h8-v6sm458701wmc.16.2018.05.15.06.49.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 15 May 2018 06:49:36 -0700 (PDT) From: luca.boccassi@gmail.com To: Beilei Xing Cc: Qi Zhang , dpdk stable Date: Tue, 15 May 2018 14:47:20 +0100 Message-Id: <20180515134731.9337-69-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180515134731.9337-1-luca.boccassi@gmail.com> References: <20180503110612.12146-2-luca.boccassi@gmail.com> <20180515134731.9337-1-luca.boccassi@gmail.com> Subject: [dpdk-stable] patch 'net/i40e: print original value for global register change' has been queued to stable release 18.02.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 May 2018 13:49:37 -0000 Hi, FYI, your patch has been queued to stable release 18.02.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/16/18. So please shout if anyone has objections. Thanks. Luca Boccassi --- >>From 0e18c22790b425a70d8c08ddcb27353437f3997e Mon Sep 17 00:00:00 2001 From: Beilei Xing Date: Sat, 12 May 2018 02:17:07 +0800 Subject: [PATCH] net/i40e: print original value for global register change [ upstream commit 3d4faec9857f04dd25130ab51e356209b2559a39 ] Currently, only new value is printed during global register change. Add original value to help debugging facility. Fixes: bc66b9717c50 ("net/i40e: add debug logs when writing global registers") Signed-off-by: Beilei Xing Acked-by: Qi Zhang --- drivers/net/i40e/i40e_ethdev.c | 56 +++++++++++++++++++++++++++++++++--------- drivers/net/i40e/i40e_ethdev.h | 8 +++--- 2 files changed, 49 insertions(+), 15 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index c1550ff07..4f4456d4a 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -656,12 +656,16 @@ rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev, } static inline void -i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) +i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr, + uint32_t reg_val) { + uint32_t ori_reg_val; + + ori_reg_val = i40e_read_rx_ctl(hw, reg_addr); i40e_write_rx_ctl(hw, reg_addr, reg_val); - PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " - "with value 0x%08x", - reg_addr, reg_val); + PMD_DRV_LOG(DEBUG, + "Global register [0x%08x] original: 0x%08x, after: 0x%08x", + reg_addr, ori_reg_val, reg_val); } RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd); @@ -1117,6 +1121,30 @@ i40e_support_multi_driver(struct rte_eth_dev *dev) return 0; } +static int +i40e_aq_debug_write_global_register(struct i40e_hw *hw, + uint32_t reg_addr, uint64_t reg_val, + struct i40e_asq_cmd_details *cmd_details) +{ + uint64_t ori_reg_val; + int ret; + + ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL); + if (ret != I40E_SUCCESS) { + PMD_DRV_LOG(ERR, + "Fail to debug read from 0x%08x", + reg_addr); + return -EIO; + } + + PMD_DRV_LOG(DEBUG, + "Global register [0x%08x] original: 0x%"PRIx64 + ", after: 0x%"PRIx64, + reg_addr, ori_reg_val, reg_val); + + return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details); +} + static int eth_i40e_dev_init(struct rte_eth_dev *dev) { @@ -1224,7 +1252,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) /* initialise the L3_MAP register */ if (!pf->support_multi_driver) { - ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40), + ret = i40e_aq_debug_write_global_register(hw, + I40E_GLQF_L3_MAP(40), 0x00000028, NULL); if (ret) PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", @@ -3381,7 +3410,8 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev, return 0; } - ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id), + ret = i40e_aq_debug_write_global_register(hw, + I40E_GL_SWT_L2TAGCTRL(reg_id), reg_w, NULL); if (ret != I40E_SUCCESS) { PMD_DRV_LOG(ERR, @@ -3393,6 +3423,8 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev, "Global register 0x%08x is changed with value 0x%08x", I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w); + i40e_global_cfg_warning(I40E_WARNING_TPID); + return 0; } @@ -3441,7 +3473,6 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev, /* If NVM API < 1.7, keep the register setting */ ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type, tpid, qinq); - i40e_global_cfg_warning(I40E_WARNING_TPID); return ret; } @@ -8268,7 +8299,8 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len) } if (reg != val) { - ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2), + ret = i40e_aq_debug_write_global_register(hw, + I40E_GL_PRS_FVBM(2), reg, NULL); if (ret != 0) return ret; @@ -9161,11 +9193,11 @@ i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val) { uint32_t reg = i40e_read_rx_ctl(hw, addr); - PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg); if (reg != val) - i40e_write_global_rx_ctl(hw, addr, val); - PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr, - (uint32_t)i40e_read_rx_ctl(hw, addr)); + i40e_write_rx_ctl(hw, addr, val); + PMD_DRV_LOG(DEBUG, + "Global register [0x%08x] original: 0x%08x, after: 0x%08x", + addr, reg, (uint32_t)i40e_read_rx_ctl(hw, addr)); } static void diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index a51bd4b07..e6b08e0ad 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -81,11 +81,13 @@ #define I40E_WRITE_GLB_REG(hw, reg, value) \ do { \ + uint32_t ori_val; \ + ori_val = I40E_READ_REG((hw), (reg)); \ I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \ (reg)), (value)); \ - PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \ - "with value 0x%08x", \ - (reg), (value)); \ + PMD_DRV_LOG(DEBUG, "global register [0x%08x] " \ + "original: 0x%08x, after: 0x%08x ", \ + (reg), (ori_val), (value)); \ } while (0) /* index flex payload per layer */ -- 2.14.2