From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by dpdk.org (Postfix) with ESMTP id 756B18E5E for ; Sun, 20 May 2018 15:09:35 +0200 (CEST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 23C1F21DCC; Sun, 20 May 2018 09:09:35 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute1.internal (MEProxy); Sun, 20 May 2018 09:09:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fridaylinux.org; h=cc:date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=ddfXNiUoidMvQHY+m 8OXx8KQioWujMKMwoUYrVo3wkk=; b=ZQSDSzbbTTLOUdgXGgd/jkVMIzgTg/ptJ ACDg/1CJyfxUWg5EZ+vTz34xqNk1/RKktOdNKWpIySzh66f+I+ZBhzXw+yublq5b 7Xs1IOGa9IdMIGxkU1XV11en7NiqWKh7wlmQZDxMhEVJYNzP3RgOgAAxnDv7/iqu ewyAhdcv1v/PREio3SMz3yFmzjpvL3zoVDMwMqaFM4Op2+mI2Q2gs5f5Av6CWBaA E2WzwZSJja5EDhBxP2mGwMej615cfjGL3q1SyivJ2dKBfMmbDkNfkXFQNyKNLARV +jJaPcVkB0xxpiainHchF8/y8U0Bjepl/Jpk/4ULMDIL5xBJ7Q4jA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=ddfXNiUoidMvQHY+m8OXx8KQioWujMKMwoUYrVo3wkk=; b=GFaZI4wd cf1Z23mXMUBiN/ZdFaN5sjrSXQV5Zh8WQc4AbwcCmUAXWd1glNRBK+tmE4A+Mz45 YdSoFxbxS6/6PostfbyM0v5khzUyOpp4geoCRtCHywDeP45sTJyTx97zH2G5ArCI UX6wZtppBrbNBtj54lje9FN+C+mJuY5yFMlyIZAejNyuYhcQ+j1hA7DxLtVVcGSP eHmkcDe2pfax/AIxVqeWGITPt1QRvQhJbqBxWBDMvwQQtCLo16GaIFI4mtqHwsG/ r6JficUITRrW5lGzxyi0r/jgnyfQj7pz2fjnKRAjfRewspxFW3t9BbCC2VH6PLJD RZ7AIVSy7Ro/vQ== X-ME-Proxy: X-ME-Proxy: X-ME-Proxy: X-ME-Proxy: X-ME-Proxy: X-ME-Proxy: X-ME-Sender: Received: from yuanhanliu-NB0.tencent.com (unknown [223.74.148.80]) by mail.messagingengine.com (Postfix) with ESMTPA id 0A59510263; Sun, 20 May 2018 09:09:32 -0400 (EDT) From: Yuanhan Liu To: Wenzhuo Lu Cc: Michael Luo , Qi Zhang , dpdk stable Date: Sun, 20 May 2018 21:02:46 +0800 Message-Id: <20180520130246.16287-30-yliu@fridaylinux.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180520130246.16287-1-yliu@fridaylinux.org> References: <20180520130246.16287-1-yliu@fridaylinux.org> Subject: [dpdk-stable] patch 'net/ixgbe: fix too many interrupts' has been queued to LTS release 17.11.3 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 20 May 2018 13:09:35 -0000 Hi, FYI, your patch has been queued to LTS release 17.11.3 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/27/18. So please shout if anyone has objections. Thanks. --yliu --- >>From a4826c103d5853bec25493b1e68f2f254b506428 Mon Sep 17 00:00:00 2001 From: Wenzhuo Lu Date: Thu, 17 May 2018 13:34:09 +0800 Subject: [PATCH] net/ixgbe: fix too many interrupts [ upstream commit 874f79102d2a15dd50293082842006fbc06572c7 ] To support kernel VF, PBA bit is always set. But it may cause the too many interrupts issue on specific Linux kernel versions, e.g. 4.4.0-116. PF host should set the auto clean, mask and throttling as we always set the register for kernel VF. Fixes: 6b75183ac4d0 ("net/ixgbe: fix wrong PBA setting") Signed-off-by: Michael Luo Signed-off-by: Wenzhuo Lu Reviewed-by: Qi Zhang --- drivers/net/ixgbe/ixgbe_ethdev.c | 49 +++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 249b6926e..71f1c1260 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -5836,8 +5836,12 @@ ixgbe_configure_msix(struct rte_eth_dev *dev) /* won't configure msix register if no mapping is done * between intr vector and event fd + * but if misx has been enabled already, need to configure + * auto clean, auto mask and throttling. */ - if (!rte_intr_dp_is_en(intr_handle)) + gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); + if (!rte_intr_dp_is_en(intr_handle) && + !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) return; if (rte_intr_allow_others(intr_handle)) @@ -5861,27 +5865,30 @@ ixgbe_configure_msix(struct rte_eth_dev *dev) /* Populate the IVAR table and set the ITR values to the * corresponding register. */ - for (queue_id = 0; queue_id < dev->data->nb_rx_queues; - queue_id++) { - /* by default, 1:1 mapping */ - ixgbe_set_ivar_map(hw, 0, queue_id, vec); - intr_handle->intr_vec[queue_id] = vec; - if (vec < base + intr_handle->nb_efd - 1) - vec++; - } + if (rte_intr_dp_is_en(intr_handle)) { + for (queue_id = 0; queue_id < dev->data->nb_rx_queues; + queue_id++) { + /* by default, 1:1 mapping */ + ixgbe_set_ivar_map(hw, 0, queue_id, vec); + intr_handle->intr_vec[queue_id] = vec; + if (vec < base + intr_handle->nb_efd - 1) + vec++; + } - switch (hw->mac.type) { - case ixgbe_mac_82598EB: - ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, - IXGBE_MISC_VEC_ID); - break; - case ixgbe_mac_82599EB: - case ixgbe_mac_X540: - case ixgbe_mac_X550: - ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); - break; - default: - break; + switch (hw->mac.type) { + case ixgbe_mac_82598EB: + ixgbe_set_ivar_map(hw, -1, + IXGBE_IVAR_OTHER_CAUSES_INDEX, + IXGBE_MISC_VEC_ID); + break; + case ixgbe_mac_82599EB: + case ixgbe_mac_X540: + case ixgbe_mac_X550: + ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); + break; + default: + break; + } } IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF); -- 2.11.0