From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by dpdk.org (Postfix) with ESMTP id C25012BF3 for ; Wed, 23 May 2018 16:33:54 +0200 (CEST) Received: by mail-wm0-f68.google.com with SMTP id j5-v6so9816595wme.5 for ; Wed, 23 May 2018 07:33:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p3cigxyDNVot9t0ZaTsLMSCKS6IED+/WcIVkpAPfe4g=; b=tB6OhIcxY5jNhz55o04Djq9SRYQbWA1gjSsHTUse7NUo2ikw205MIZskbSRga7bX4N kNtgPyGsdZ7CKqdYEXeAjQNPITFwHRbvjSNCwiIUC/WICtym1xnxwFxQrPLPRyrPIQdx nPJXqai2PRRHOBvxM5QnQsDqRD3oA+HtRcBkVyXKlgnSVsNqlCqQgxeugsl/EwogIoyG frSBeugLzVnHOTwCQZRbqlQwBmc3zgcwDOfw/GWcTX+rR+fUQGKGxoSRpUkzwur/Rp7z 6CdufxN80ARUg/btwjPBp+peo/t/asiD++uAgXnrOwD8JI/RNa7QJjLXJKXV9JKsJduB XmPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p3cigxyDNVot9t0ZaTsLMSCKS6IED+/WcIVkpAPfe4g=; b=tGVZsje4Kz8IR+kLJHKDAuime4PTXXTtgTLWcwEF1DNn7YXYDMA6DxQ5iQiB8ZbZBs V/9TZIP6j8R07TAF7NDnfr4fRsZ7MX4Pngh/0lMtXZeFP74zP2Knk1c440O1sm51LOpW zK8oeVtombib04R0d8ZuCu2+8rAaWOcrx7ky8yWFERVlt4G5yYcZ9s4nWwH6Hg5Z87Zy rg75Zr+cSLp2SL0BmrHquB7SgqTKPnfrpgsqvlf2hRXbp6nbKuDTLvxSZHC4KZYUm6j1 14EJS4Fx0W7fmLYvyViEapN1xqEzadhUec4n/+xoqAht8Srp4dfaSyqXrdO0h9BUpRYE 8hug== X-Gm-Message-State: ALKqPwcZvTp9d4/bBonyMQNXx4TRfEY4O0lmW7wzKSK/gY+B6RWjRZM2 MuitSLKsvZGKwftsApG5XE8= X-Google-Smtp-Source: AB8JxZqLkoMluEfrFa1a3P9d8x8XbtZmdp1HJtWPlnnzjAGuqfna5eIWXCdCGowiy1jW1TPsJSNTlA== X-Received: by 2002:a1c:800e:: with SMTP id b14-v6mr4750300wmd.143.1527086034209; Wed, 23 May 2018 07:33:54 -0700 (PDT) Received: from localhost ([2a00:23c5:be9a:5200:ce4c:82c0:d567:ecbb]) by smtp.gmail.com with ESMTPSA id m9-v6sm29723374wrf.72.2018.05.23.07.33.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 23 May 2018 07:33:53 -0700 (PDT) From: luca.boccassi@gmail.com To: Wenzhuo Lu Cc: Michael Luo , Qi Zhang , dpdk stable Date: Wed, 23 May 2018 15:33:23 +0100 Message-Id: <20180523143344.16885-2-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20180523143344.16885-1-luca.boccassi@gmail.com> References: <20180516100945.4449-2-luca.boccassi@gmail.com> <20180523143344.16885-1-luca.boccassi@gmail.com> Subject: [dpdk-stable] patch 'net/ixgbe: fix too many interrupts' has been queued to LTS release 16.11.7 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 May 2018 14:33:54 -0000 Hi, FYI, your patch has been queued to LTS release 16.11.7 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/25/18. So please shout if anyone has objections. Thanks. Luca Boccassi --- >>From beb1dc15572d3f729568f2d6de315a8f57486df6 Mon Sep 17 00:00:00 2001 From: Wenzhuo Lu Date: Thu, 17 May 2018 13:34:09 +0800 Subject: [PATCH] net/ixgbe: fix too many interrupts [ upstream commit 874f79102d2a15dd50293082842006fbc06572c7 ] To support kernel VF, PBA bit is always set. But it may cause the too many interrupts issue on specific Linux kernel versions, e.g. 4.4.0-116. PF host should set the auto clean, mask and throttling as we always set the register for kernel VF. Fixes: 6b75183ac4d0 ("net/ixgbe: fix wrong PBA setting") Signed-off-by: Michael Luo Signed-off-by: Wenzhuo Lu Reviewed-by: Qi Zhang --- drivers/net/ixgbe/ixgbe_ethdev.c | 49 +++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 6444a6ce2..d3cfdc189 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -5422,8 +5422,12 @@ ixgbe_configure_msix(struct rte_eth_dev *dev) /* won't configure msix register if no mapping is done * between intr vector and event fd + * but if misx has been enabled already, need to configure + * auto clean, auto mask and throttling. */ - if (!rte_intr_dp_is_en(intr_handle)) + gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); + if (!rte_intr_dp_is_en(intr_handle) && + !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) return; if (rte_intr_allow_others(intr_handle)) @@ -5447,27 +5451,30 @@ ixgbe_configure_msix(struct rte_eth_dev *dev) /* Populate the IVAR table and set the ITR values to the * corresponding register. */ - for (queue_id = 0; queue_id < dev->data->nb_rx_queues; - queue_id++) { - /* by default, 1:1 mapping */ - ixgbe_set_ivar_map(hw, 0, queue_id, vec); - intr_handle->intr_vec[queue_id] = vec; - if (vec < base + intr_handle->nb_efd - 1) - vec++; - } + if (rte_intr_dp_is_en(intr_handle)) { + for (queue_id = 0; queue_id < dev->data->nb_rx_queues; + queue_id++) { + /* by default, 1:1 mapping */ + ixgbe_set_ivar_map(hw, 0, queue_id, vec); + intr_handle->intr_vec[queue_id] = vec; + if (vec < base + intr_handle->nb_efd - 1) + vec++; + } - switch (hw->mac.type) { - case ixgbe_mac_82598EB: - ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, - IXGBE_MISC_VEC_ID); - break; - case ixgbe_mac_82599EB: - case ixgbe_mac_X540: - case ixgbe_mac_X550: - ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); - break; - default: - break; + switch (hw->mac.type) { + case ixgbe_mac_82598EB: + ixgbe_set_ivar_map(hw, -1, + IXGBE_IVAR_OTHER_CAUSES_INDEX, + IXGBE_MISC_VEC_ID); + break; + case ixgbe_mac_82599EB: + case ixgbe_mac_X540: + case ixgbe_mac_X550: + ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); + break; + default: + break; + } } IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF); -- 2.14.2